PDSP16116MC Zarlink Semiconductor, PDSP16116MC Datasheet - Page 15

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PDSP16116MC

Manufacturer Part Number
PDSP16116MC
Description
16 by 16 Bit Complex Multiplier
Manufacturer
Zarlink Semiconductor
Datasheet
two PDSP1601As must be used (controlled by the same logic)
or a single PDSP1601/A could be used handling real and
imaginary data on alternate cycles (using the same
instructions for both cycles).
Fig.8. Only 4 bit data paths are used in calculating the shift.
This means that we must be able to trap very small values
negative of GWR and force a 15-bit right shift in such cases.
As FFT data consists of real and imaginary parts, either
An example of an output normalisation circuit is shown in
UNVERSAL
EXPONENT
4-BIT SUBTRACTOR
Fig.9 Output Normalisation Circuitry
WTOUT
4-BIT ADDER
NORMALISED OUTPUT DATA
4-BIT MUX
SV-PORT
GWR
PDSP1601
N.B.
the purpose of determing the shift required, instead of
modifying it according to Table.6. To compensate for this, the
Universal Exponent may be increased by one.
C-PORT
It is easier to simply add the word tag to the exponent for
1111
sign bit
16-BIT DATA
B-PORT
IS
ASRSV
PDSP16116/A/MC
15

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