PDSP16116MC Zarlink Semiconductor, PDSP16116MC Datasheet - Page 14

• Manufacturer Part Number: PDSP16116MC
• Description: 16 by 16 Bit Complex Multiplier
• Manufacturer: Zarlink Semiconductor

PDSP16116/A/MC
Control of the FFT
of the data, the following signals are provided :
and when each pass is complete. Fig.7 shows how these
signals should be used and a commentary is provided below.
high (where it will remain for the duration of the pass).
should be pulled low during the initial cycle when the first data
words A and B are presented to the inputs of the butterfly
processor. The following cycle
FFT Output Normalisation
display, storage or transmission, it is essential that all results
are compatible, i.e. with the binary point in the same position.
However, in order to preserve the dynamic range of the data
in the FFT calculation, the PDSP1601/A employs a range of
different weightings. Therefore, data must be re-formatted at
the end of the FFT to be pre-determined common weighting.
This can be done by comparing the exponent of given data
word with the pre-determined unversial exponent and then
shifting the data word by the difference. The PDSP1601/A,
with its multifunction 16 bit barrel shifter, is ideally suited to this
task.
according to theory, the largest possible data result from an
FFT is N times the largest input data. This means that the
binary point can move a maximum of log2(N) places to the
right. Hence, if we choose the Unverisal Exponent to be
log2(N) this should give us sufficient range to represent all
data points faithfully.
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A, B, W, WTA, WTB
To enable the block floating point hardware to keep track
These inform the PDSP16116/A when an FFT is starting
To commence the FFT, the signal
When an FFT system outputs a series of FFT results for
What value should the Unversal Exponent take? Well,
A', B', WTOUT
SOBFP
EOBFP
EOPSS
GWR
CLK
- start of the FFT
- end of current pass
1
1 1
start of first pass
2
3
4
5
1
6
must be pulled high
2
7
Figure 8 - Use of the BFP Control Signals
3
should be set
n-1
n-5
n
n-4
n-3
end of first pass / start of next pass
(minimum number of lay cycles shown)
- period between other intermediate passes
is similar
n-2
where it should remain for the duration of the FFT. New data
is presented to the processor each successive cycle until the
end of the first pass of the FFT. On the last cycle of the pass,
the signal
minimum of five cycles *, the time required to clear the pipeline
of the butterfly processor so that all the results from one pass
are obtained before commencing the following pass. On the
initial cycle of each new pass, the signal
pulled high and it should remain high until the final cycle of that
pass, when it is pulled low again.
arrange the data for the next pass, for example, then
may be kept low as long as necessary - the next pass cannot
commence until it is brought high again.
cal maximum. Hence, it may be worthwhile to try various
Unverisal Exponents and choose the one best suited to the
particular application.
exponent: the 5-bit GWR applicable to all data words from a
given FFT and a 2-bit WTOUT associated with each individual
data word. To find the complete exponent for a given word, the
GWR for that FFT must be modified by its WTOUT as shown
in Table 6. The result is the number of places the binary point
has shifted to the right during the course of the FFT.
to determine the shift required. This is done by subtracting it
from the Unversial Exponent. The number of places to be
shifted is equal to the difference between the two exponents.
The shift can be implemented in a PDSP1601/A. The shift
value is fed into the SV port.
n-1
* Should a longer pause be required between passes - to
In practice, data output may never approach the theoreti-
Data is output from the butterfly processor with a two-part
This value must be compared with the Unversial Exponent
n
1
2
should be pulled low and remain low for a
3
4
5
1
6
2
7
1 = first cycle of
n = last cycle of
data in pass
data in pass
should be