DSP56300 Motorola Inc, DSP56300 Datasheet - Page 10

• Manufacturer Part Number: DSP56300
• Description: DSP56301 Digital Signal Processor
• Manufacturer: Motorola Inc

Errata
Number
ED30
ED31
ED32
DSP56301 Errata
 1996-2002, Motorola
Document Update
Description (added 9/12/1997; identified as a Documentation
errata 2/1/99):
When the ESSI transmits data in the On-Demand mode (i.e., MOD
= 1 in CRB and DC[4:0] = $00000 in CRA) with WL[2:0] = 100, the
transmission does not work properly.
Workaround:
To ensure correct operation, do not use the On-Demand mode with
the
WL[2:0] = 100 32-bit Word-Length mode.
Description (added 9/12/1997; modified 9/15/1997; identified as
a Documentation errata 2/1/99):
Programming the ESSI to use an internal frame sync (i.e., SCD2 = 1
in CRB) causes the SC2 and SC1 signals to be programmed as
outputs. If however, the corresponding multiplexed pins are
programmed by the Port Control Register (PCR) to be GPIOs, then
the GPIO Port Direction Register (PRR) chooses their direction, but
this causes the ESSI to use an external frame sync if GPI is selected.
Note: This errata and workaround apply to both ESSI0 and ESSI1.
Workaround:
To assure correct operation, either program the GPIO pins as
outputs or configure the pins in the PCR as ESSI signals.
Note: The default selection for these signals after reset is GPI.
Description (added 11/9/98; identified as a Documentation errata
2/1/99):
When returning from a long interrupt (by RTI instruction), and the
first instruction after the RTI is a move to a DALU register (A, B, X,
Y), the move may not be correct, if the 16-bit arithmetic mode bit
(bit 17 of SR) is changed due to the restoring of SR after RTI.
Workaround:
Replace the RTI with the following sequence:
movec
nop
rti
Freescale Semiconductor, Inc.
DSP56301 Digital Signal Processor
For More Information On This Product,
ssl,sr
301CE2K30A_0_8
Go to: www.freescale.com
Mask:2K30A
Chip Errata
ng 12/19/02 pg. 10
Applies
to Mask
2K30A
2K30A
2K30A