DSP56300 Motorola Inc, DSP56300 Datasheet - Page 3

• Manufacturer Part Number: DSP56300
• Description: DSP56301 Digital Signal Processor
• Manufacturer: Motorola Inc

Errata
Number
ED4
ED6
ED7
ED8
DSP56301 Errata
 1996-2002, Motorola
Document Update
Description (added 10/09/1997):
The following instructions should not start at address LA:
MOVE to/from Program space {MOVEM, MOVEP (only the P
space options)}
This is not a bug but a documentation update (Appendix B,
DSP56300 Family Manual).
Description (added 4/13/98):
When the HIRQ pin is used in pulse mode (HIRH=0 in DCTR), the
LT[7:0] value (in CLAT) should not be zero. This is not a bug but a
documentation update.
Description (added 1/27/98):
When activity passes from one DMA channel to another and the
DMA interface accesses external memory (which requires one or
more wait states), the DACT and DCH status bits in the DMA
Status Register (DSTR) may indicate improper activity status for
DMA Channel 0 (DACT = 1 and DCH[2:0] = 000).
Workaround:
None.
Pertains to: DSP56300 Family Manual, Sections 8.1.6.3 and 8.1.6.4
Description (added 10/09/1997):
The timing for HSAK is no longer qualified by the data strobe. The
new timing numbers are:
a. T318—HSAK assertion from HA0–HA10 and HAEN valid is
b. T319—HSAK assertion hold from HA0-HA10 and NAEN not
This is not a bug, but a documentation update of a specification
change.
30.0 ns maximum.
valid is 2.0 ns minimum.
Freescale Semiconductor, Inc.
DSP56301 Digital Signal Processor
For More Information On This Product,
301CE2K30A_0_8
Go to: www.freescale.com
Mask:2K30A
Chip Errata
ng 12/19/02 pg. 3
Applies
to Mask
2K30A
2K30A
2K30A
2K30A