DSP56371D Motorola Inc, DSP56371D Datasheet - Page 7

• Manufacturer Part Number: DSP56371D
• Description: high density CMOS device
• Manufacturer: Motorola Inc

9.0
MOTOROLA
No.
10
11
12
13
14
15
16
17
18
19
Delay from RESET assertion to all output
pins at reset value
Required RESET duration
Syn reset setup time from RESET
Syn reset de assert delay time
Mode select setup time
Mode select hold time
Minimum edge-triggered interrupt request
assertion width
Minimum edge-triggered interrupt request
deassertion width
Delay from interrupt trigger to interrupt
code execution.
Duration of level sensitive IRQA assertion
to ensure interrupt service (when exiting
Stop)
Reset, Stop, Mode Select, and Interrupt Timing
•
•
•
•
•
•
•
•
•
2, 3
Power on, external clock
generator, PLL disabled
Power on, external clock
generator, PLL enabled
Maximum
Minimum
Maximum(PLL enabled)
PLL is active during Stop and Stop
delay is enabled
(OMR Bit 6 = 0)
PLL is active during Stop and Stop
delay is not enabled
(OMR Bit 6 = 1)
PLL is not active during Stop and
Stop delay is enabled (OMR Bit 6
= 0)
PLL is not active during Stop and
Stop delay is not enabled (OMR
Bit 6 = 1)
Table 6 Reset, Stop, Mode Select, and Interrupt Timing
Characteristics
3
Freescale Semiconductor, Inc.
For More Information On This Product,
4
DSP56371 Technical Data
Go to: www.freescale.com
Reset, Stop, Mode Select, and Interrupt Timing
9+(128KxT
(25 x T
(2xT
9+(128K× T
Expression
10 xT
25× T
2 x T
2 x T
2× T
2 xT
2 xT
C
T
)+T
—
C
C
C
)+T
C
C
C
C
C
C
+ 5
LOCK
C
)+T
lock
C
)
lock
Min
11.1
11.1
11.1
10.0
10.0
11.1
11.1
60.0
704
138
5.0
5.7
—
—
5
Max
5.5
11
—
—
—
—
—
—
—
—
--
Unit
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
7