UPD160040 NEC, UPD160040 Datasheet - Page 4

• Manufacturer Part Number: UPD160040
• Description: 384-OUTPUT TFT-LCD SOURCE DRIVER
• Manufacturer: NEC

4. PIN FUNCTIONS
4
S
D
D
D
D
D
D
R,/L
STHR
STHL
CLK
STB
SRC
ORC
POL
Pin Symbol
1
00
10
20
30
40
50
to S
to D
to D
to D
to D
to D
to D
384
07
17
27
37
47
57
Driver
Port 1 display data
Port 2 display data
Shift direction control
Right shift start pulse
Left shift start pulse
Shift clock
Latch
Through rate control
Output resistance control
Polarity input
Pin Name
Output
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Data Sheet S15859EJ1V0DS
The D/A converted 256-gray-scale analog voltage is output.
The display data is input with a width of 48 bits, viz., the gray scale data
(8 bits) by 6 dots (2 pixels).
D
The shift direction control pin of shift register. The shift directions of the
shift registers are as follows.
R,/L = H (right shift): STHR input, S
R,/L = L (left shift): STHL input, S
These are the start pulse input/output pins when connected in cascade.
Loading of display data starts when a H level is read at the rising edge
of CLK.
A H level should be input at the pulse of one cycle of the clock signal.
If the start pulse input is more than 2 CLK, the first 1 CLK of the H-level
input is valid.
For right shift, STHR is input and STHL is output.
For left shift, STHL is input and STHR is output.
The shift clock input pin of shift register. The display data is loaded into
the data register at the rising edge.
When 66-clock pulses are input after input of the start pulse, input of
display data is halted automatically. The contents of the shift register
are cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch circuit at
the rising edge. In addition, at the falling edge, the gray scale voltage is
supplied to the driver. It is necessary to ensure input of one pulse per
horizontal period.
SRC = H: High-through-rate period (large current consumption)
SRC = L: Low-through-rate period (small current consumption)
SRC is pulled up to the V
ORC = H: Low output resistance period
ORC = L: High output resistance period
ORC is pulled up to the V
POL = L: The S
output uses V
POL = H: The S
output uses V
S
of the POL signal is allowed the setup time (t
STB’s rising edge.
When it switches such as POL = H L or L H, all output pins are
output reset during STB = H. When it does not switch, all output pins
become Hi-Z (high impedance) during STB = H. Refer to 7.
RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL, AND
OUTPUT WAVEFORM for details.
2n 1
X0
: LSB, D
indicates the odd output and S
X7
: MSB
8
0
-V
-V
2n 1
2n 1
15
7
as the reference supply.
as the reference supply.
output uses V
output uses V
DD1
DD1
in the IC.
in the IC.
Description
0
384
8
-V
-V
1
2n
7
15
as the reference supply. The S
S
indicates the even output. Input
S
as the reference supply. The S
1
384
, STHR output
, STHL output
POL–STB
www.DataSheet4U.com
) with respect to
PD160040
(1/2)
2n
2n