UPD160061A NEC, UPD160061A Datasheet - Page 4

• Manufacturer Part Number: UPD160061A
• Description: 384-OUTPUT TFT-LCD SOURCE DRIVER
• Manufacturer: NEC

4. PIN FUNCTIONS
4
S
D
D
D
D
D
D
R,/L
STHR
STHL
CLK
STB
POL
POL21,
POL22
LPC,
HPC
Pin Symbol
1
00
10
20
30
40
50
to S
to D
to D
to D
to D
to D
to D
384
05
15
25
35
45
55
Shift direction control
Driver output
Display data input
Right shift start pulse
input/output
Left shift start pulse
input/output
Shift clock input
Latch input
Polarity input
Data inversion input
Bias current control
input
Pin Name
Output The D/A converted 64-gray-scale analog voltage is output.
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2
pixels).
D
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
R,/L = H (right shift): STHR input, S
R,/L = L (left shift): STHL input, S
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
When right shift: STHR input, STHL output
When left shift: STHL input, STHR output
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more than 2CLK, the first 1CLK of the high-level input is valid.
Refers to the shift register’s shift clock input. The display data is incorporated into the data
register at the rising edge. At the rising edge of the 64th after the start pulse input, the start
pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If
66th clock pulses are input after input of the start pulse, input of display data is halted
automatically. The contents of the shift register are cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch circuit at the rising edge. And, at
the falling edge of the STB, the gray scale voltage is supplied to the driver. When STB = H
period, driver output level is Hi-Z (High impedance).
It is necessary to ensure input of one pulse per horizontal period.
POL = L: The S
POL = H: The S
S
allowed the setup time (t
Data inversion can invert when display data is loaded.
POL21: D
POL22: D
POL21, POL22 = H: Data inversion loads display data after inverting it.
POL21, POL22 = L: Data inversion does not invert input data.
Please refer to panel loads and driver power supply voltage (V
Refer to 10. BIAS CURRENT CONTROL BY LPC AND HPC. LPC pin is pulled down to the
V
2n−1
SS1
X0
: LSB, D
inside the IC, HPC pin is pulled up to the V
indicates the odd output, and S
Data Sheet S16041EJ2V0DS
V
V
00
30
9
4
X5
to D
to D
as the reference supply.
as the reference supply.
: MSB
2n–1
2n–1
05
35
, D
, D
output uses V
output uses V
10
40
to D
to D
POL
15
45
-
STB
, D
, D
) with respect to STB’s rising edge.
20
50
384
0
5
to D
to D
to V
to V
1
→S
→S
2n
25
55
4
indicates the even output. Input of the POL signal is
9
1
, data inversion can invert display data
, data inversion can invert display data
384
, STHR output
as the reference supply. The S
as the reference supply. The S
Description
, STHL output
DD1
inside the IC.
DD2
), when set up these pins.
www.DataSheet4U.com
µ
PD160061A
2n
2n
output uses V
output uses V
5
(1/2)
0
to
to