LM3S102-IRN20(T) Luminary Micro, Inc., LM3S102-IRN20(T) Datasheet - Page 115

• Manufacturer Part Number: LM3S102-IRN20(T)
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

October 6, 2006
Reset
Reset
Type
Type
Bit/Field
31:8
GPIO Masked Interrupt Status (GPIOMIS)
Offset 0x418
7:0
RO
RO
31
15
0
0
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
GPIOMIS is the state of the interrupt after masking.
RO
RO
30
14
0
0
reserved
Name
MIS
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0x00
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
0: Corresponding GPIO line interrupt not active.
1: Corresponding GPIO line asserting interrupt.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
MIS
RO
RO
19
0
3
0
LM3S102 Data Sheet
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
115