LM3S102-IRN20(T) Luminary Micro, Inc., LM3S102-IRN20(T) Datasheet - Page 13

• Manufacturer Part Number: LM3S102-IRN20(T)
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Register 5:
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Register 14:
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Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 264
Register 1:
Register 2:
Register 3:
Register 4:
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Register 15:
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Analog Comparator ...................................................................................................................... 296
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Pin Diagram ................................................................................................................................... 307
October 6, 2006
SSI Clock Prescale (SSICPSR), offset 0x010 ......................................................................... 247
SSI Interrupt Mask (SSIIM), offset 0x014 ................................................................................ 248
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .................................................................... 249
SSI Masked Interrupt Status (SSIMIS), offset 0x01C.............................................................. 250
SSI Interrupt Clear (SSIICR), offset 0x020.............................................................................. 251
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0.................................................. 252
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4.................................................. 253
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8.................................................. 254
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ................................................. 255
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0.................................................. 256
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4.................................................. 257
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8.................................................. 258
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ................................................. 259
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0..................................................... 260
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4..................................................... 261
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8..................................................... 262
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC .................................................... 263
I2C Master Slave Address (I2CMSA), offset 0x000 ................................................................ 275
I2C Master Control/Status (I2CMCS), offset 0x004................................................................. 276
I2C Master Data (I2CMDR), offset 0x008................................................................................ 281
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00........................................ 300
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04.............................................. 301
Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ................................................ 302
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ............................ 303
Analog Comparator Status 0 (ACSTAT0), offset 0x20 ............................................................ 304
Analog Comparator Control 0 (ACCTL0), offset 0x24 ............................................................. 305
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Timer Period (I2CMTPR), offset 0x00C ................................................................ 282
C Master Interrupt Mask (I2CMIMR), offset 0x010 ............................................................... 283
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ...................................................... 284
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ................................................ 285
C Master Interrupt Clear (I2CMICR), offset 0x01C ............................................................... 286
C Master Configuration (I2CMCR), offset 0x020 .................................................................. 287
C Slave Own Address (I2CSOAR), offset 0x000 .................................................................. 288
C Slave Control/Status (I2CSCSR), offset 0x004 ................................................................. 289
C Slave Data (I2CSDR), offset 0x008................................................................................... 291
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ................................................................. 292
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010......................................................... 293
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014................................................... 294
C Slave Interrupt Clear (I2CSICR), offset 0x018 .................................................................. 295
Preliminary
LM3S102 Data Sheet
13