LM3S328 Luminary Micro, Inc., LM3S328 Datasheet - Page 12

• Manufacturer Part Number: LM3S328
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

List of Registers
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Analog-to-Digital Converter (ADC).............................................................................................. 196
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 226
Register 1:
12
Watchdog Control (WDTCTL), offset 0x008............................................................................ 178
Watchdog Interrupt Clear (WDTICR), offset 0x00C ................................................................ 179
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ....................................................... 180
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014.................................................. 181
Watchdog Lock (WDTLOCK), offset 0xC00 ............................................................................ 182
Watchdog Test (WDTTEST), offset 0x418 .............................................................................. 183
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0..................................... 184
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4..................................... 185
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8..................................... 186
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .................................... 187
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ..................................... 188
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ..................................... 189
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ..................................... 190
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................... 191
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0........................................ 192
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4........................................ 193
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8........................................ 194
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ...................................... 195
ADC Active Sample Sequencer (ADCACTSS), offset 0x000 .................................................. 202
ADC Raw Interrupt Status (ADCRIS), offset 0x004................................................................. 203
ADC Interrupt Mask (ADCIM), offset 0x008 ............................................................................ 204
ADC Interrupt Status and Clear (ADCISC), offset 0x00C........................................................ 205
ADC Overflow Status (ADCOSTAT), offset 0x010 .................................................................. 206
ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ...................................................... 207
ADC Underflow Status (ADCUSTAT), offset 0x018 ................................................................ 208
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020.................................................. 209
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ..................................... 210
ADC Sample Averaging Control (ADCSAC), offset 0x030 ...................................................... 211
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040.................. 212
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044............................................. 214
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048.................................... 216
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C................................ 217
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060.................. 218
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064............................................. 219
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068.................................... 219
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C................................ 219
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080.................. 220
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084............................................. 221
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088.................................... 221
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C................................ 221
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ................. 222
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x064............................................. 223
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ................................... 223
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................... 223
ADC Test Mode Loopback (ADCTMLB), offset 0x100 ............................................................ 224
UART Data (UARTDR), offset 0x000 ...................................................................................... 233
Preliminary
October 8, 2006