LM3S328 Luminary Micro, Inc., LM3S328 Datasheet - Page 330

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LM3S328

Manufacturer Part Number
LM3S328
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet

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Signal Tables
16
Table 16-1. Signals by Pin Number (Sheet 1 of 3)
330
Number
Pin
10
12
13
14
15
16
17
11
1
2
3
4
5
6
7
8
9
Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register (see page 120).
Important:
Table 16-1 shows the pin-to-signal-name mapping, including functional characteristics of the
signals. Table 16-2 lists the signals in alphabetical order by signal name. Table 16-3 groups the
signals by functionality, except for GPIOs. Table 16-4 lists the GPIO pins and their alternate
functionality.
ADC0
ADC1
ADC2
ADC3
RST
LDO
VDD
GND
OSC0
OSC1
PC7
CCP4
PC6
CCP3
PC5
CCP1
PC4
VDD
GND
PA0
U0Rx
Pin Name
All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins
(PB7 and PC[3:0]) which default to the JTAG functionality.
I/O
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
-
-
-
I
-
-
I
TTL
Analog
Analog
Analog
Analog
Analog
Analog
Buffer
Power
Power
Power
Power
Power
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Preliminary
Analog-to-digital converter input 0.
Analog-to-digital converter input 1.
Analog-to-digital converter input 2.
Analog-to-digital converter input 3.
System reset input.
The low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 μF or greater.
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Oscillator crystal output.
GPIO port C bit 7.
Timer 2 capture input, compare output, or PWM output channel 4.
GPIO port C bit 6.
Timer 1 capture input, compare output, or PWM output channel 3.
GPIO port C bit 5.
Timer 0 capture input, compare output, or PWM output channel 1.
GPIO port C bit 4.
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
GPIO port A bit 0.
UART0 receive data input.
Oscillator crystal input or an external clock reference input.
Description
October 8, 2006

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