UPD753012GC NEC, UPD753012GC Datasheet - Page 15
UPD753012GC
Manufacturer Part Number
UPD753012GC
Description
4-BIT SINGLE-CHIP MICROCONTROLLER
Manufacturer
NEC
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4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE
4.1 Differences between Mk I Mode and Mk II Mode
mode can be switched by the bit 3 of the stack bank select register (SBS).
The CPU of PD753017 has the following two modes: Mk I and Mk II, either of which can be selected. The
• Mk I mode:
• Mk II mode:
Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL
Program memory (bytes)
Number of stack bytes
for subroutine instructions
BRA !addr1 instruction
CALLA !addr1 instruction
CALL !addr instruction
CALLF !faddr instruction
series. This mode enhances the software compatibility with products which have more
than 16K bytes.
When Mk II mode is selected, the number of stack bytes (usable area) in the execution
of a subroutine call instruction increases by 1 per stack compared to Mk I mode.
Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction
takes another machine cycle. Therefore, when more importance is attached to RAM
utilization or throughput than software compatibility, use the Mk I mode.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Upward compatible with PD75316B.
Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes.
Incompatible with PD75316B.
Can be used in all the 75XL CPU’s including those products whose ROM capacity is more
than 16K bytes.
•
•
2 bytes
Not available
3-machine cycles
2-machine cycles
PD753012 : 12288
PD753016, 753017 : 16384
Mk I Mode
PD753012, 753016, 753017
•
•
•
3 bytes
Available
4-machine cycles
3-machine cycles
PD753012 : 12288
PD753016 : 16384
PD753017 : 24576
Mk II Mode
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