AN1212 Freescale Semiconductor / Motorola, AN1212 Datasheet - Page 18

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AN1212

Manufacturer Part Number
AN1212
Description
J1850 Multiplex Bus Communication Using the MC68HC705C8 and the SC371016 J1850 Communications Interface (JCI)
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
AN1212/D
18
RECEIVE BUFFER POINTER
LOGIC "1", NEGATING THE
MODE, CPOL = CPHA = 1,
CORRECT RESET VALUE
SET PORT C, BIT 1 TO A
SPI ENABLED, MASTER
RECEIVE BUFFER INTO
LOCATION "txcntrl", ITS
AND RESET OUTPUTS
INITIALIZE SPCR FOR
NEGATIVE EDGE IRQ
LOCATION OF EACH
RESETTING THE JCI
BITS 0 AND 1, AS CS
LOAD $40 INTO RAM
JCI’S RESET INPUT,
INITIALIZE PORT C,
BIT RATE = 500 kHz
INITIALIZE OPTION
CORRESPONDING
RAM0 = RAM1 = 1
LOAD STARTING
REGISTER FOR
SUBROUTINE
CALL JCIRST
J1850 Multiplex Bus Communication Using the MC68HC705C8
and the SC371016 J1850 Communications Interface (JCI)
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 9. JCIRST Subroutine
NO
NO
Go to: www.freescale.com
MASK REGISTER VALUE
byte" BIT COMBINATION
INTO SPDR, INITIATING
LOCATION "data": INTO
LOCATION "command"
LOCATION "command"
LOAD ACCEPTANCE
LOAD BYTE IN RAM
LOAD BYTE IN RAM
LOAD "load as AMR
SPDR, INITIATING
LOCATION "data"
INTO MCU RAM
INTO MCU RAM
SPI TRANSFER
SPI TRANSFER
SPI TRANSFER
SPI TRANSFER
COMPLETE?
COMPLETE?
YES
YES
IS
IS
NO
NO
CODE REGISTER VALUE
byte" BIT COMBINATION
INTO SPDR, INITIATING
LOCATION "data": INTO
LOCATION "command"
LOCATION "command"
LOAD ACCEPTANCE
LOAD BYTE IN RAM
LOAD BYTE IN RAM
LOAD "load as ACR
SPDR, INITIATING
LOCATION "data"
INTO MCU RAM
INTO MCU RAM
RETURN FROM
SPI TRANSFER
SPI TRANSFER
SPI TRANSFER
SPI TRANSFER
SUBROUTINE
COMPLETE?
COMPLETE?
YES
YES
IS
IS
MOTOROLA

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