AN1212 Freescale Semiconductor / Motorola, AN1212 Datasheet - Page 20

• Manufacturer Part Number: AN1212
• Description: J1850 Multiplex Bus Communication Using the MC68HC705C8 and the SC371016 J1850 Communications Interface (JCI)
• Manufacturer: Freescale Semiconductor / Motorola

AN1212/D
20
PREVIOUS Tx COMPLETED, NO NEW
MESSAGE AVAILABLE; txi BIT SET BY
TIMER INTERRUPT SREVICE ROUTINE
TO INDICATE NO PENDING Tx
PREVIOUS Tx COMPLETED, AVAILABLE
MESSAGE ISNOW TRANSFERRED FROM
HOST TO JCI; txt BIT CLEARED BY TIMER
INTERRUPT SERVICE ROUTINE TO
INDICATE NO NEW MESSAGE AVIALABLE
Figure 10. Transmit Double Semaphore State Sequence
J1850 Multiplex Bus Communication Using the MC68HC705C8
and the SC371016 J1850 Communications Interface (JCI)
has completed updating this data or not. Therefore, the user must ensure that
the "txt" bit is cleared before updating data in the host MCU RAM transmit
buffer.
Refer to
bits, and what events cause each bit to be set and cleared.
If the user’s application requires the use of more than one RAM transmit buffer,
a transmit queue can easily be set up to transmit messages to the JCI, either
in FIFO order, or by priority of the message.
If the host MCU wishes to transmit a message as soon as possible, the Tx
buffer in the JCI can be cleared by calling the TXFLUSH subroutine. This
subroutine will command the JCI to immediately empty the Tx buffer, preparing
it for another message from the host. If the JCI is attempting to transmit when
the Tx buffer is flushed, the JCI will abort the transmission, ensuring that the
transmission halts on a non-byte boundary.
Figure 11
Figure 12
between the host MCU and the JCI.
check the status of the JCI.
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 10
shows the sequence of the example transmit routine, while
outlines the steps necessary for the actual message transfer
Go to: www.freescale.com
for a graphical representation of the use of the semaphore
INITIAL STATE
txi = 1
txt = 0
txi = 0
txt = 0
txi = 0
txt = 1
Figure 13
PREVIOUS Tx PENDING, MESSAGE IS
NOT TRANSFERRED FROM HOST TO JCI;
txt BIT SET BY "TRANSMIT" SUBROUTINE
CALLED BY USER’S APPLICATION
SOFTWARE TO INDICATE THAT THE
NEXT MESSAGE IS AVAILABLE
NO Tx PENDING, NEW MESSAGE IS
TRANSFERRED FROM HOST TO JCI;
txi BIT CLEARED BY "TRANSMIT"
SUBROUTINE CALLED BY USER’S
APPLICATION SOFTWARE TO INDICATE
PENDING Tx
shows the sequence used to
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