AN1212 Freescale Semiconductor / Motorola, AN1212 Datasheet - Page 19

• Manufacturer Part Number: AN1212
• Description: J1850 Multiplex Bus Communication Using the MC68HC705C8 and the SC371016 J1850 Communications Interface (JCI)
• Manufacturer: Freescale Semiconductor / Motorola

Transmitting
MOTOROLA
J1850 Multiplex Bus Communication Using the MC68HC705C8
and the SC371016 J1850 Communications Interface (JCI)
Transmitting a message to the JCI for transmission onto the MUX bus simply
requires the host MCU to store the message bytes in the correct RAM location
and call the TRANSMIT subroutine. The software handles moving the data
from the host MCU to the JCI and determining when the message has been
transmitted successfully.
When the host MCU has data to be transmitted onto the MUX bus, the
’Message of Tx’ bit (labeled "txt") in the RAM location "txcntrl" should first be
cleared. This will ensure that a partial message will not inadvertently be
transferred to the JCI. The host then stores the message bytes including the
header bytes, into RAM, beginning at location "txbuf". The number of bytes in
the message is then loaded into the RAM location "txcount". The host then calls
the subroutine TRANSMIT. This subroutine will check the status of the JCI to
determine whether the previous message has been transmitted and, if so, will
transmit the new
message bytes to the JCI for transmission onto the MUX bus and then clear the
’Previous Tx Complete’ bit (labeled "txi"). If the previous message has not
completed transmission, the TRANSMIT subroutine will set the "txt" bit in the
RAM location "txcntrl", and then call a timer subroutine called TIMERSU which
enables a timer interrupt to check the JCI status at regular intervals. The
TRANSMIT subroutine will then return to the main application routine.
The TIMERSU subroutine reads the current value of the timer’s free-running
counter, adds a value approximately equal to the shortest valid multiplex frame
length, stores the new value in the output compare register, and enables the
output compare interrupt. When the counter reaches the output compare value,
an interrupt of the CPU occurs. The timer interrupt service routine then checks
the status of the JCI. If the previous message has still not completed
transmission, the output compare value advance sequence is repeated, and
the JCI status is regularly checked, until the current message in the JCI is
transmitted onto the MUX bus or is discarded due to reaching the retry limit.
Once the timer interrupt routine determines that the JCI’s Tx buffer is empty,
the routine checks to see if the "txt" it is set in RAM location "txcntrl". If this bit
is set, indicating that a new message is ready for transmission, the "txt" bit is
cleared, and the message bytes are transferred to the JCI for transmission, and
the timer reset sequence continues.
If the "txt" bit is clear, the timer interrupt routine sets the "txi" bit, and disables
the timer interrupt. In this way, bits "txt" and "txi" in RAM location "txcntrl" act
as a double semaphore to track the status of both the JCI Tx buffer and the
transmit buffer in host MCU RAM, allowing the software to automatically
transfer messages to the JCI whenever the Tx buffer in the JCI can accept
them.
If the timer interrupt occurs while the host is loading message data into its
transmit buffer and the "txt" bit has not been cleared by the user, the number of
bytes in RAM location "txcount" will be transferred to the JCI, whether the host
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MC68HC705C8/JCI Interface Driver Routines
AN1212/D
19