UPD75P3036 NEC, UPD75P3036 Datasheet - Page 46

• Manufacturer Part Number: UPD75P3036
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER
• Manufacturer: NEC

46
Data retention characteristics of data memory in STOP mode and at low supply voltage
(T
Notes 1.
Data retention timing (when STOP mode released by RESET)
RESET
Data retention timing (standby release signal: when STOP mode released by interrupt signal)
Release signal setup time
Oscillation stabilization
wait time
Standby release signal
A
V
= –40 to +85 C)
(interrupt request)
V
DD
DD
2.
Note 1
STOP instruction execution
Parameter
STOP instruction execution
The oscillation stabilization wait time is the time during which the CPU stops operating to prevent
unstable operation when oscillation is started.
Set by the basic interval timer mode register (BTM). (Refer to the table below.)
BTM3
–
–
–
–
BTM2
0
0
1
1
t
t
SREL
WAIT
BTM1
Symbol
0
1
0
1
BTM0
0
1
1
1
Released by RESET
Released by interrupt request
V
Data retention mode
Data retention mode
STOP mode
V
DDDR
STOP mode
DDDR
2
2
2
2
20
17
15
13
/f
/f
/f
/f
X
X
X
X
f
(approx. 250 ms)
(approx. 31.3 ms)
(approx. 7.81 ms)
(approx. 1.95 ms)
X
Conditions
= 4.19 MHz
Wait Time
Internal reset operation
t
2
2
2
2
t
SREL
SREL
20
17
15
13
/f
/f
/f
/f
X
X
X
X
MIN.
(approx. 175 ms)
(approx. 21.8 ms)
(approx. 5.46 ms)
(approx. 1.37 ms)
f
X
0
Oscillation stabilization wait time
= 6.0 MHz
Oscillation stabilization wait time
t
t
WAIT
WAIT
Note 2
2
TYP.
15
/f
X
MAX.
Operation mode
Operation mode
PD75P3036
Unit
ms
ms
s