UPD78320GJ-5BJ NEC, UPD78320GJ-5BJ Datasheet
UPD78320GJ-5BJ
Related parts for UPD78320GJ-5BJ
UPD78320GJ-5BJ Summary of contents
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... A/D converter • Watchdog timer Powerful serial interface (with an on-chip dedicated baud rate generator) • UART • SBI (NEC Standard Serial Bus Interface) • 3-wire serial I/O APPLICATIONS Motor control devices Unless there are any particular notices, the PD78322 is described as the representative model in this document. ...
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ORDERING INFORMATION Part Number PD78320GF-3B9 80-pin plastic QFP (14 PD78320GJ-5BJ 74-pin plastic QFP (20 PD78320L 68-pin plastic QFJ ( PD78322GF- -3B9 80-pin plastic QFP (14 PD78322GJ- -5BJ 74-pin plastic QFP (20 PD78322L- 68-pin plastic QFJ ( Remark indicates ROM code ...
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PIN CONFIGURATION • 68-pin plastic QFJ ( 950 mil) PD78320L PD78322L P30 P31 P32/SO/SB0 12 P33/SI/SB1 13 P34/SCK 14 P80/TO00 15 P81/TO01 16 P82/TO02 17 P83/TO03 18 P84/TO10 19 P85/TO11 20 RESET ...
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... P54/A12 10 P55/A13 P56/A14 13 P57/A15 P70/AN0 17 P71/AN1 Caution The NC pin should be connected PD78320, 78322 for noise control (can also be left open). ...
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... NC 15 P85/TO11 16 RESET WDTO 21 RTP0/P00 RTP1/P01 Caution The NC pin should be connected to V PD78320, 78322 P72/AN2 P71/AN1 61 60 P70/AN0 P57/A15 57 56 P56/A14 55 P55/A13 ...
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... Turbo Mode TAS : Turbo Access Strobe WR : Write Strobe RD : Read Strobe ASTB : Address Strobe AD0 to AD7 : Address/Data Bus A8 to A15 : Address Bus AN0 to AN7 : Analog Input AV : Analog Reference Voltage REF AV : Analog Analog Power Supply Ground Non-connection ...
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... Realtime output port Serial interface with a dedicated baud rate generator Serial communication • UART interface • SBI (NEC Serial Bus Interface channel A/D converter 10-bit resolution (8 analog inputs) • External : 8, internal Interrupt • 3 servicing modes (vectored interrupt function, context switching function, and macro service function) ...
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DIFFERENCES BETWEEN PD78322 AND 78320 Product Name Item Internal ROM Input I/O line Input /output Specifiable as I 8-bit unit. Port 4 Functions as multiplexed address/data buses (AD0 to AD7) in the external memory expansion (P40 to P47) ...
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NMI PROGRAMMABLE INTERRUPT CONTROLLER INTP0–INTP5 (P21–P26) (P80) TO00 (P81) TO01 TIMER/COUNTER UNIT (P82) TO02 (REALTIME PULSE UNIT) (P83) TO03 (P84) TO10 (P85) TO11 (P27) TI/INTP6 (P34) SCK (P32) SO/SB0 SERIAL INTERFACE (SBI) (P33) SI/SB1 (UART) (P30 ...
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... LIST OF PIN FUNCTIONS ..................................................................................................................... 12 1.1 PORT PINS ...................................................................................................................................................... 12 1.2 NON-PORT PINS ............................................................................................................................................. 13 1.3 PIN INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ................... 15 2. CPU ARCHITECTURE ............................................................................................................................ 17 2.1 MEMORY SPACE ............................................................................................................................................ 17 2.2 PROCESSOR REGISTERS ............................................................................................................................ 20 2.2.1 Control Registers ........................................................................................................................... 21 2.2.2 General Registers ........................................................................................................................... 23 2.2.3 Special Function Registers (SFR) ................................................................................................ 25 2.3 DATA MEMORY ADDRESSING ..................................................................................................................... 30 2.3.1 General Register Addressing ....................................................................................................... 30 2.3.2 Short Direct Addressing ................................................................................................................ 30 2.3.3 Special Function Register (SFR) Addressing ............................................................................ 30 3 ...
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PACKAGE DRAWINGS .......................................................................................................................... 75 11. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 78 APPENDIX A. LIST OF 78K/ SERIES PRODUCTS ................................................................................ 79 APPENDIX B. TOOLS .................................................................................................................................. 81 B.1 DEVELOPMENT TOOL ................................................................................................................................... 81 B.2 EVALUATION TOOL ....................................................................................................................................... 85 B.3 EMBEDDED SOFTWARE ............................................................................................................................... 85 ...
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LIST OF PIN FUNCTIONS 1.1 PORT PINS Pin Name I/O Port 0 Input/ 8-bit input/output port P00 to P07 output Input/output can be specified bit-wise Also serves as a realtime output port. P20 P21 P22 P23 Port 2 Input ...
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NON-PORT PINS (1/2) Pin Name I/O Realtime output port which generates pulses in synchronization with the trigger signal RTP0 to RTP7 Output transmitted from the realtime pulse unit (RPU). Nonmaskable interrupot request input capable of specifying the effective at ...
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... AV — A/D converter GND SS RESET Input System reset input X1 Input Crystal connect pin for sysem clock oscillation. When an external clock is supplied, the clock is input to X1 and the inverted clock is input to X2. (X2 can also be left open.) X2 — Positive power supply V –– GND pin — ...
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... PIN INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The pin input/output circuits, partly simplified, are shown in Table 1-1 and Figure 1-1. Table 1-1. I/O Circuit Types of Pins and their Recommended Pin P00 to P07/RTP0 to RTP7 P20/NMI P21 to P26/INTP0 to INTP5 P27/INTP6/TI P30 P31 P32/SO/SB0 ...
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Type P-ch IN N-ch Type 2 IN Schmitt-triggered input having hysteresis characteristics. Type P-ch N-ch Type 4 data output disable Push-pull output which can become high-impedance output (with both P-ch and N-ch set to ...
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CPU ARCHITECTURE 2.1 MEMORY SPACE In the PD78322 a maximum of 64K bytes of memory can be addressed (see Figure 2-1). Program fetches can be performed within the area from 0000H to FDFFH. However, when external memory expansion is ...
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... The external access area is mapped in the FFD0H to FFDFH 16-byte area of the special function register (SFR). In this way, the external memory can be accessed by SFR addressing. Dedicated pins (TAS and TMD pins) are provided to connect turbo access manager ( PD71P301) PD71P301 is used, the program processing speed equal to that of the internal ROM can be obtained. ...
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PD78322) FFFFH Special Function Register (SFR) (256 FF00H FEFFH Main RAM (256 FE00H Data Memory FDFFH Peripheral RAM (384 FC80H FC7FH Memory Space (64K 8) Program Memory External Memory Data Memory (48256 4000H 3FFFH Program Memory ...
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PROCESSOR REGISTERS The processor registers consist mainly of three groups. They are general registers consisting of 8 banks of sixteen 8- bit registers, control registers consisting of one 8-bit register and three 16-bit registers, and special function registers such ...
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Control Register The control registers carry out dedicated functions such as control of the program sequence, status and stack memory, and modification of operand addressing. They consist of three 16-bit registers and one 8-bit register. (1) Program counter (PC) ...
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Auxiliary carry flag (AC carry is generated out of bit result of operation or a borrow is generated into bit 3, this flag is set all other cases, this flag is ...
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CPU control word (CCW) This is an 8-bit register consisting of CPU control related flags mapped in the special function register area and can be controlled by the software. All bits are reset RESET ...
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The sixteen 8-bit registers can function as eight 16-bit register pairs (RP0 to RP7) as well. As shown in Table 2-1, the sixteen 8-bit registers are characterized by functional names. The X register functions as the lower half of the ...
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Special Function Registers (SFR) These registers are provided with special functions. They include various peripheral hardware mode registers and control registers (CCW). The special function registers are assigned in the FF00H to FFFFH 256-byte space. Short direct memory addressing ...
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Table 2-2. List of Special Function Registers (1/4) Address Special Function Register (SFR) Name FF00H Port 0 FF02H Port 2 FF03H Port 3 FF04H Port 4 FF05H Port 5 FF07H Port 7 FF08H Port 8 FF09H Port 9 FF0AH Free ...
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Table 2-2. List of Special Function Registers (2/4) Address Special Function Register (SFR) Name FF36H Capture register 03 Note FF37H (higher 16 bits) FF38H Capture/compoare register X0 Note FF39H (higher 16 bits) FF3AH Capture/compoare register 01 Note FF3BH (higher 16 ...
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Table 2-2. List of Special Function Registers (3/4) Address Special Function Register (SFR) Name Asynchronous serial interface mode FF88H register Asynchronous serial interface status FF8AH register FF8CH Serial receive buffer FF8EH Serial send shift register FFB0H Timer control register FFB1H ...
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Table 2-2. List of Special Function Registers (4/4) Address Special Function Register (SFR) Name FFF0H Context switching enable register 0L FFF1H Context switching enable register 0H FFF2H Context switching enable register 1L FFF3H –– FFF4H External interupt mode register 0 ...
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General Register Addressing The general registers consist of eight register banks, each consisting of sixteen 8-bit registers or eight 16-bit registers. General register addressing is carried out using the register specify field bits supplied from ...
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... BUS CONTROL UNIT (BCU) In the BCU, the necessary bus cycle is started according to the physical address obtained by the execution unit (EXU bus cycle startup request is made from the EXU, a prefetch address is generated and instruction prefetch is carried out. The prefetched operation code is fetched into the instruction queue. ...
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PORT FUNCTIONS Table 3-1 lists the digital input/output ports. Each port can carry out many control operations including 8 and other bit data input/output manipulations. Table 3-1. Port Functions and Features Port Name Function Specifiable bit-wise for input/output. Port ...
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... Internal system clock frequency CLK The system clock oscillator oscillates by a crystal resonator connected to X1 and X2 pins. It stops oscillating when set to the standby mode (STOP). External clocks can be input to the system clock oscillator. In such cases, input a clock signal to the X1 pin and input the inverted clock signal to the X2 pin ...
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... Keep the wiring as short as possible. • Do not cross any other signal lines, and keep clear of lines in which a high fluctuating current flows. • Ensure that oscillator capacitor connection points are always at the same potential not ground in a ground pattern in which a high current flows. ...
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... This unit can measure pulse intervals and frequencies, and generate programmable pulse outputs. It consists mainly of two timers. To flexibly cope with many applications, the configuration of registers connected to the timers can be changed using programs. To meet various applications, toggle output (6 max.) or set/reset output (4 max.) can be selected as timer output ...
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TM0 CLK 16/18-BIT FREE RUNNING TIMER f /8 CLK 0 COMPARE REG. CM00 COMPARE REG. CM01 COMPARE REG. CM02 COMPARE REG. CM03 INTP0 CAPTURE REG. CT01 INTP1 INTP2 CAPTURE REG. CT02 INTP3 CAPTURE REG. ...
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Realtime Output Function The realtime output port can set/reset port outputs bit-wise in synchronization with the trigger signal transmitted from the RPU (Realtime Pulse Unit). It enables to generate multi-channel synchronous pulses easily. WR PORT WR RTPR RTPR n ...
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A/D CONVERTER The PD78322 incorporates a high-speed, high-resolution 10-bit analog/digital (A/D) converter. This A/D converter is equipped with eight analog inputs (AN0 to AN7) and A/D conversion result register (ADCR) which holds the conversion results. Upon termination of conversion, ...
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RXB Receive Buffer R D Shift Register Receive Control Parity Check INTSR 1 16 Figure 3-6. Asynchronous Serial Interface Block Diagram Internal Bus RXE PS1 PS0 ASIS TXS OVE Shift Register Send Control INTSER ...
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Figure 3-7. Block Diagram of Clocked Serial Interface 8 CSIM MOD2 CTXE CRXE WUP MOD1 CLS1 CLS0 SI/SB1 SO/SB0 N-ch Open-Drain Output Enable SCK Internal Bus MOD0 RELT SET CLEAR SO Latch Shift Register SIO D Q Bus Release/ Command/Acknowledge ...
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WATCHDOG TIMER The watchdog timer is used to prevent program overrun and deadlock. Normal operation of the program or system can be confirmed by checking that no watchdog timer interrupt has been generated. Thus, an instruction to clear the ...
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INTERRUPT FUNCTIONS 4.1 OVERVIEW In the PD78322, various interrupt requests generated externally or from the on-chip peripheral hardware are handled in the following three servicing modes. Interrupt Request Interrupt requests are classified into the following three groups. • Nonmaskable ...
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Interrupt Default Request Type Priority Request Signal ––– ––– Software ––– ––– ––– NMI Non- maskable ––– INTWDT 0 INTOV 1 INTP0 2 INTP1 3 INTP2 4 INTP3 5 INTP4/INTCCX0 6 INTP5/INTCC01 7 INTP6/TI 8 INTCM00 Maskable 9 INTCM01 10 ...
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MACRO SERVICE The macro service function is executed at the interrupt request to carry out data operation and data transfer in hardware terms between the special function register area and the memory space. Upon startup of the macro service, ...
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CONTEXT SWITCHING FUNCTION This is the function to first select the specified register bank in hardware terms by generating an interrupt request or executing BRKCS instruction, to branch the selected register bank to the vector address prestored in the ...
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Context Switching Function by BRKCS Instruction The context switching function can be started by executing BRKCS instruction. The context switched register bank is specified by the lower 3-bit immediate data of the 2nd operation code of BRKCS instruction. When ...
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STANDBY FUNCTIONS The PD78322 has the standby function to decrease the power consumption of the system. The following two modes are available for execution of the standby function. • HALT mode ........ Mode for halting the CPU operation clock. ...
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... AD to AD7 A8 to A15 RD WR PD78320, 78322 Remarks P92 P93 General- External device purpose port connection mode PD71P301 TAS TMD connection mode Remarks P92 P93 PD78322 TAS TMD emulation mode General- External device purpose port connection mode PD71P301 TAS TMD connection mode ...
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OPERATION AFTER RESET If the RESET input pin is set to the low level, the system reset is applied and each hardware becomes as initialized status (reset status). If RESET input becomes high level, the reset state is released ...
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INSTRUCTION SET This chapter covers instruction operations. For the operation codes and the number of instruction execution clock cycles, see PD78322 User’s Manual (IEU-1248). (1) Operand identifier and description method In each instruction operand field, enter the operand using ...
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Mnemonic Operand r1, #byte saddr, #byte Note sfr , #byte saddr saddr, A saddr, saddr A, sfr sfr mem MOV mem [saddrp] [saddrp !addr16 !addr16, A PSWL, #byte PSWH, ...
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Mnemonic Operand rp1, #word saddrp, #word sfrp, #word rp, rp1 AX, saddrp saddrp, AX saddrp, saddrp MOVW AX, sfrp sfrp, AX rp1, !addr16 !addr16, rp1 AX, mem mem, AX AX, saddrp AX, sfrp XCHW saddrp, saddrp rp,rp1 AX, mem A, ...
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Mnemonic Operand A, #byte saddr, #byte 3 (saddr), CY sfr, #byte 4 sfr saddr SUB A, sfr saddr, saddr 3 (saddr mem ...
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Mnemonic Operand A, #byte saddr, #byte sfr, #byte saddr OR A, sfr saddr, saddr A, mem mem #byte saddr, #byte sfr, #byte r, r1 XOR A, saddr A, sfr saddr, saddr A, mem mem, A ...
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Mnemonic Operand AX, #word 3 AX, CY saddrp, #word 4 (saddrp), CY sfrp, #word 5 sfrp, CY ADDW rp, rp1 2 rp, CY AX, saddrp 2 AX, CY AX, sfrp 3 AX, CY saddrp, saddrp 3 (saddrp), CY AX, #word ...
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Mnemonic Operand r1 INC saddr r1 DEC saddr rp2 INCW saddrp rp2 DECW saddrp r1, n ROR r1, n ROL r1, n RORC r1, n ROLC r1, n SHR r1, n SHL rp1, n SHRW rp1, n SHLW [rp1] ROR4 ...
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Mnemonic Operand CY, saddr. bit 3 CY CY, sfr. bit 3 CY CY, A. bit 2 CY CY, X. bit 2 CY CY, PSWH. bit 2 CY CY, PSWL. bit 2 CY MOV1 saddr. bit (saddr.bit) sfr. bit, ...
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Mnemonic Operand CY, saddr. bit CY, sfr. bit CY, A. bit XOR1 CY, X. bit CY, PSWH. bit CY, PSWL. bit saddr. bit sfr. bit A. bit SET1 X. bit PSWH. bit PSWL. bit saddr. bit sfr. bit A. bit ...
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Mnemonic Operand !addr16 CALL !addr11 CALLF [addr5] CALLT rp1 CALL [rp1] BRK RET RETB RETI sfrp PUSH post PSW PUSHU post sfrp POP post PSW POPU post SP, #word MOVW SP INCW SP DECW sfr CHKL ...
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Mnemonic Operand !addr16 rp1 BR [rp1] $ addr16 BC $ addr16 BL BNC $ addr16 BNL BZ $ addr16 BE BNZ $ addr16 BNE BV $ addr16 BPE BNV $ addr16 BPO BN $ addr16 BP $ addr16 BGT $ ...
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Mnemonic Operand PC saddr.bit, $ addr16 4 PC sfr.bit, $ addr16 4 PC A.bit, $ addr16 3 BTCLR PC X.bit, $ addr16 3 PC PSWH.bit, $ addr16 3 PC PSWL.bit, $ addr16 3 PC saddr.bit, $ addr16 4 PC sfr.bit, ...
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Mnemonic Operand [ MOVM [DE – [ [ MOVBK [DE – ], [HL – XCHM [DE – [ [ XCHBK ...
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Mnemonic Operand [ [ CMPBKC [DE – ], [HL – CMPMNC [DE – [ [ CMPBKNC [DE – ], [HL – ] STBC, #byte MOV ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T A Parameter Symbol V DD Supply voltage Input voltage V I Output voltage V O Output current low I OL Output current high I OH Analog input voltage V ...
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OSCILLATOR CHARACTERISTICS (T Resonator Recommended Circuit X2 X1 Ceramic resonator or crystal resonator C2 X1 HCMOS Invertor External clock or X1 Open HCMOS Invertor Caution When using the system clock oscillation circuit, wire the part encircled in the dotted line ...
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RECOMMENDED OSCILLATOR CONSTANT Ceramic Resonator Manufacturer Product Name CSA8.00MT CSA12.0MT CSA14.74MXZ040 CSA16.00MX040 Murata Mfg. Co., Ltd. CST8.00MTW CST12.0MTW CST14.74MXW0C3 CST16.00MXW0C3 Crystal Resonator Manufacturer Product Name HC49/U-S Kinseki Co., Ltd. HC49/U 66 Frequency Recommended Constant [MHz] C1 [pF] 8.0 30 12.0 ...
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DC CHARACTERISTICS (T = – Parameter Symbol Input voltage low IH1 Input voltage high V IH2 Output voltage low V OL Output voltage high V OH Input leakage current I LI Output ...
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... AC CHARACTERISTICS (T = – Non-consecutive read/write operation (with general-purpose memory connected) Parameter System clock cycle time Address setup time (vs. ASTB ) Address hold time (vs. ASTB ) RD delay time from address Address float time from RD Data input time from address Data input time from RD RD delay time from ASTB Data hold time (vs ...
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DEPENDENT BUS TIMING DEFINITION CYK Parameter t 0.5T – 30 SAST t 0.5T – 30 HSTA t T – 40 DAR t (2 – 90 DAID t (1 – 75 DRID t 0.5T ...
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SERIAL OPERATION (T = – Parameter Symbol Serial clock cycle time t CYSK Serial clock low-level width t WSKL Serial clock high-level width t WSKH SI setup time (vs. SCK ) t SRXSK SI hold ...
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A/D CONVERTER CHARACTERISTICS (T Parameter Symbol Resolution Note 1 Total error Quantization error Conversion time t CONV Sampling time t SAMP Note 1 Zero scale error Note 1 Full scale error Note 1 Non-linear error Note 2 Analog input voltage ...
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Non-Consecutive Read Operation t CYK (CLK) P50-P57 (Output) t SAST Hi-Z Lower Address P40-P47 (Output) (Input/ Output) t WSTH ASTB (Output) RD (Output) t DAR Non-Consecutive Write Operation (CLK) P50-P57 (Output) t SAST P40-P47 Lower Address (Input/ (Output) Output) t ...
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Serial Operation SCK t DSKTX SO SI Interrupt Input Timing NMI INTPn Remark CYSK t WSKH t WSKL t SRXSK t HSKRX t t WNIH WNIL 0. WInH WInL PD78320, ...
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Reset Input Timing RESET TI Pin Input Timing WRSH WRSL 0. WTIH WTIL PD78320, 78322 ...
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PACKAGE DRAWINGS 68 PIN PLASTIC QFJ ( 950 mil NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition ...
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PIN PLASTIC QFP ( 20 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition ...
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PIN PLASTIC QFP (14 20 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition ...
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RECOMMENDED SOLDERING CONDITIONS The PD78322 should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document “Semiconductor Device Mounting Technology Manual” (IE-1207). For soldering methods and ...
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APPENDIX A. LIST OF 78K/ SERIES PRODUCTS (1/2) PD78322 Basic instruction Minimum instruction execution time 250 ns (at 16 MHz operation) ROM 16384 Internal memory RAM Memory space Input 16 (including 8 analog inputs) I/O lines Output I/O 39 Real-time ...
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LIST OF 78K/ SERIES PRODUCTS (2/2) PD78322 Test source Internal : 1 Instructions for PD78312 and 78310 Instruction set significantly added. • On-chip watchdog timer • Standby function (STOP/HALT) Pulse unit • 68-pin plastic QFJ ( Package • 74-pin plastic ...
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APPENDIX B. TOOLS B.1 DEVELOPMENT TOOLS The following development tools are available for system development using the PD78322. Language Processor 78K/III series relocatable assembler Refers to the relocatable assembler which can be used commonly for the 78K/III (RA78K/III) series. Equipped ...
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... PA-78P322GJ ... For PD78P322GJ PA-78P322K ... For PD78P322K PA-78P322KC ... For PD78P322KC PA-78P322KD ... For PD78P322KD PA-78P322L ... For PD78P322L Connects PG-1500 and host machine via a serial and parallel interface, and controls the PG-1500 on the host machine. Host Machine OS PC-9800 series MS-DOS IBM PC/AT and its PC DOS ...
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... The IE-78327-R can be used commonly for both the PD78322 subseries and the PD78328 subseries. The IE-78320-R can be used for the PD78322 subseries. EP-78320GF-R These are the emulation probes for connecting the IE-78327-R or IE-78320 EP-78320GJ-R target system. EP-78320L-R EP-78320GF-R: for 80-pin plastic QFP ...
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... PA-78P322GF PA-78P322KC PA-78P322GJ PA-78P322L PA-78P322KD Note The socket is supplied with the emulation probe. Remark It is also possible to use the host machine and the PG-1500 by connecting them directly by the RS-232C. Emulation probes RS-232-C EP-78320GF-R EP-78320L-R EP-78320GJ-R PROM programmer Socket for connecting the emulation probe ...
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... Remark When using the real-time OS RX78K/III, you need the assembler package RA78K/III (optional) as well. Host Machine By connecting to a host machine possible to evaluate the functions equipped by the PD78322 in a simple manner. The command system of this product basically conforms to that of IE-78327-R and IE-78320-R ...
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Fuzzy Inference Development Support System Fuzzy knowledge data creation This program supports inputting/editing/evaluating (through simulation) of the fuzzy tools (FE9000, FE9200) knowledge data (fuzzy rules and membership functions). PC-9800 series IBM PC/AT and its compatible machine Translator (FT78K3) Note This ...
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... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices ...
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... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance ...