DS2482-100 Dallas Semiconducotr, DS2482-100 Datasheet - Page 4

• Manufacturer Part Number: DS2482-100
• Description: Single-Channel 1-Wire Master
• Manufacturer: Dallas Semiconducotr

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
PIN DESCRIPTION
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line
Oscillator Warm-Up Time
PIN
1
2
3
4
5
6
7
8
PARAMETER
Operating current with 1-Wire write byte sequence followed by continuous Read of Status register at 400kHz in Overdrive.
With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the passive pullup on
threshold V
exceed 300pF.
Active pullup guaranteed to turn on between V
Active or resistive pullup choice is configurable.
Except for t
parameters is found to be off the typical value, it is safe to assume that all of these parameters deviate from their typical value in
the same direction and by the same degree.
These values apply at full load, i.e., 1nF at standard speed and 0.3nF at Overdrive speed. For reduced load, the pulldown slew
rate is slightly faster.
Fall time high-to-low (t
Presence-pulse masking only applies to standard speed.
All I²C timing values are referred to V
Applies to SDA, SCL, and AD0, AD1.
I/O pins of the DS2482 do not obstruct the SDA and SCL lines if V
The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the V
undefined region of the falling edge of SCL.
The maximum t
A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement t
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + t
(according to the standard-mode I²C-bus specification) before the SCL line is released.
C
v2.1 are allowed.
I²C communication should not take place for the max t
PCTLZ
NAME
B
GND
SCL
SDA
AD1
AD0
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times according to I²C-bus Specification
V
IO
CC
IL1
F1
, all 1-Wire timing specifications and t
may not be reached in the available time. With Overdrive speed the capacitive load on the 1-Wire bus must not
HD
Power Supply Input
IO Driver for 1-Wire Line
Ground Reference
I²C Serial Clock Input. Must be tied to V
I²C Serial Data Input/Output. Must be tied to V
Active-low control output for an external P-channel MOSFET to provide extra power to
the 1-Wire line, e.g., for use with 1-Wire devices that require a higher current temporarily
to operate.
I²C Address Inputs. Must be tied to V
address of the device (see Figure 9).
:
DAT
has only to be met if the device does not stretch the LOW period (t
F1
) is derived from PD
SYMBOL
t
OSCWUP
t
BUF
C
b
IHmin
and V
SRC
(Note 15)
(Note 16)
IL1MAX
, referenced from 0.9 × V
ILmax
APUOT
levels.
and V
4 of 21
CONDITIONS
OSCWUP
are derived from the same timing circuit. Therefore, if one of these
IH1MIN
time following a power-on reset.
CC
.
FUNCTION
CC
or GND. These inputs determine the I²C slave
CC
is switched off.
through a pullup resistor.
CC
CC
to 0.1 × V
through a pullup resistor.
MIN
1.3
CC
.
IHmin
LOW
SU
) of the SCL signal.
of the SCL signal) to bridge the
:
DAT
TYP
= 1000 + 250 = 1250ns
SU
:
DAT
³ 2 50ns must then be
MAX
400
100
UNITS
pF
µs
µs