DS2482-100 Dallas Semiconducotr, DS2482-100 Datasheet - Page 5

• Manufacturer Part Number: DS2482-100
• Description: Single-Channel 1-Wire Master
• Manufacturer: Dallas Semiconducotr

Figure 1. Block Diagram
DETAILED DESCRIPTION
The DS2482-100 is a self-timed 1-Wire master, which supports advanced 1-Wire waveform features including
standard and Overdrive speeds, active pullup, strong pullup for power delivery, and presence-pulse masking. Once
supplied with command and data, the I/O controller of the DS2482 performs time-critical 1-Wire communication
functions such as reset/presence detect cycle, read-byte, write-byte, single-bit R/W and triplet for ROM Search,
without requiring interaction with the host processor. The host obtains feedback (completion of a 1-Wire function,
presence pulse, 1-Wire short, search direction taken) through the Status register and data through the Read Data
register. The DS2482 communicates with a host processor through its I²C bus interface in standard mode or in fast
mode. The logic state of two address pins determines the I²C slave address of the DS2482, allowing up to four
devices operating on the same bus segment without requiring a hub.
DEVICE REGISTERS
The DS2482 has three registers that the I²C host can read: Configuration, Status, and Read Data. These registers
are addressed by a read pointer. The position of the read pointer, i.e., the register that the host reads in a
subsequent read access, is defined by the instruction that the has DS2482 executed last. The host has read and
write access to the Configuration register to enable certain 1-Wire features.
Configuration Register
The DS2482 supports allows four 1-Wire features that are enabled or selected through the Configuration register.
These features are:
These features can be selected in any combination. While APU, PPM, and 1WS maintain their state, SPU returns
to its inactive state as soon as the strong pullup has ended.
Configuration Register Bit Assignment
After a device reset (power-up cycle or initiated by the Device Reset command) the Configuration register reads
00h. When writing to the Configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the
one's complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
1WS
bit 7
§
§
§
§
Active Pullup (APU)
Presence Pulse Masking (PPM)
Strong Pullup (SPU)
1-Wire Speed (1WS)
DS2482-100
SPU
bit 6
SDA
SCL
AD0
AD1
PPM
bit 5
APU
bit 4
Controller
Interface
Register
Config
1WS
I²C
bit 3
SPU
bit 2
T-Time OSC
PPM
bit 1
Read Data
Controller
Register
Register
5 of 21
Status
I/O
APU
bit 0
XCVR
Line
PCTLZ
IO