AN2072 Freescale Semiconductor / Motorola, AN2072 Datasheet - Page 12

• Manufacturer Part Number: AN2072
• Description: AN2072, Decision Feedback Equalizer for StarCore-Based DSPs
• Manufacturer: Freescale Semiconductor / Motorola

Implementation of the Algorithm
matrix multiply block. If H
(H
Matrix2, four address registers are used as follows:
The matrix multiply block performs the matrix multiply operation as follows:
12
T
)
•
•
•
•
T
= H. For example, to multiply two matrices of size [(N
One address register in modulo mode, pointing to Matrix1 (moving in the direction of ptrA in Equation 24
on page 13)
One address register in linear mode, pointing to Matrix2 (moving in the direction of ptrB in Equation 24 on
page 13)
One address register in linear mode, for intermediate address calculation
One address register in linear mode, pointing to the output matrix “mult_out”
1.
2.
3.
M1
N
one row entry of the output Matrix. Two complex values are read at a time from each matrix using the
move.4f instruction and four mac operations are performed in parallel.
N
of Matrix2. Note here that pointer to Matrix1 needs to be modulo to wrap around the same row. The
pointer to Matrix2 needs to be linear to advance to the next column in Matrix2. This is shown in the
following example to demonstrate how the first row of the output is generated.
where:
Advance the pointer to the next row in the Matrix1, redefine the modulo address register, and repeat
step 2 to generate the next row of output. The final matrix is filled by rows. Before the data is written
to memory, the output of the last mac operation is scaled by a right shift of (ceiling {log
tion]}). Therefore, the amount of right shift for the implementation is four (that is, asrr #4,dn, where
dn holds the data that is written to memory). An offset greater than the modulo size cannot be added to
the modulo register, so another intermediate register (r4) is used and updated linearly to point to the
next row of Matrix1. Then the value of the intermediate register is transferred to the address register
(r0) and its corresponding base resister (r8) using the assembly instruction tfra r4,r0 and tfra r4,r8.
The hardware loop called NN_loop performs this register update in the assembly code as shown in
Code Listing 5.
f
f
R1
mac operations are performed between one row of Matrix1 and one column of Matrix2 to produce
mac operations are performed between the same previous row of the Matrix1 and the next column
M1
R1
a 1 1
a 2 1
a 3 1
a 4 1
mac M1
(
(
(
(
= Matrix1
,
,
,
,
(
) a 2 1
) a 2 2
) a 3 2
) a 4 2
Decision Feedback Equalizer for StarCore™-Based DSPs, Rev. 1
T
R1
°
°
°
(
(
(
(
is read row-wise, the result is H
,
,
,
,
,
Matrix 1
M2
Row1
) a 3 1
) a 2 3
) a 3 3
) a 4 3
C1
(
(
(
(
) mac M1
,
,
,
,
) a 4 1
) a 2 4
) a 3 4
) a 4 4
(
(
(
(
(
,
,
,
,
R1
°
°
°
,
)
)
)
)
M2
×
M2
C2
b 1 1
b 2 1
b 3 1
b 4 1
C1
(
(
(
(
) mac M1
,
,
,
,
M2
M2
) b 2 1
) b 2 2
) b 3 2
) b 4 2
(
C1
C2
T
f
(
(
(
(
+ν)
Matrix 2
= Matrix2
and if H
,
,
,
,
R1
°
°
°
,
×
) b 3 1
) b 2 3
) b 3 3
) b 4 3
M2
N
(
(
(
(
C3
f
,
,
,
,
]
T
) mac M1
×
Column l
is read column-wise, the result is
) b 4 1
) b 2 4
) b 3 4
) b 4 4
[N
(
(
(
(
f
(
,
,
,
,
×
(N
)
)
)
)
R1
°
°
°
,
=
f
+ν)], identified as Matrix1 and
M2
C4
)
Freescale Semiconductor
2
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