AN2072 Freescale Semiconductor / Motorola, AN2072 Datasheet - Page 29

• Manufacturer Part Number: AN2072
• Description: AN2072, Decision Feedback Equalizer for StarCore-Based DSPs
• Manufacturer: Freescale Semiconductor / Motorola

intermediate result (that is, the element for which 1/sqrt() is computed) in a data register instead of memory greatly
improves the accuracy of the algorithm because storing small fractional numbers to memory (16-bit) increases the
error. Keeping the result in a data register holds better precision as the data register uses 32-bit representation.
Because of error introduced in fixed-point calculations, the optimum delay may be more than one in some
situations, but they always appear next to each other. Picking any one of the columns of the L_matrix (feedback
coefficient and the corresponding feed forward coefficient) that has the same optimum delay (that lies between
N
communication systems where it is safe to assume the optimal decision delay is N
computation can be further reduced by removing the routine that locates the optimal delay. The entire process of
computing the DFE coefficient from the channel-impulse response required 7680 cycles for a DFE (8,4). In this
implementation example, the channel-impulse response length is assumed to be of length five.
5
Decision feedback equalizers are very useful as sub-optimal solutions when the constellation size is large and the
channel memory is long, which is true in many current and next-generation communications systems. That
decision feedback equalizers are implemented as FIR filters makes them especially attractive for processors such as
the SC140 core, which have multiple ALUs, because multi-sampling can be used to implement FIR filters very
efficiently. The DSP implementation of Cholesky-based DFEs is a way to find the DFE coefficients using the
concept of spectral factorization to eliminate the need for computationally expensive complex-matrix inversion.
Also, simulation results show that optimizing the decision delay improves the decision point SNR, which in turn
improves BER performance of the communication receiver. Our implementation optimizes the decision delay. The
results obtained from the real-time SC140 implementation are accurate within the precession of the 16-bit
computation.
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[1]
[2]
Freescale Semiconductor
f
–1 to N
Conclusion
References
“MMSE Decision-Feedback Equalizers: Finite-Length Results,” Al-Dhahir, N.; Cioffi, J.M. IEEE
Transactions on Information Theory. Volume: 41 4 , July 1995, pp. 961–975.
“Efficient Computation of the Delay-Optimized Finite Length MMSE-DFE, Al-Dhahir, N.; Cioffi, J.M,
IEEE Transactions on Signal Processing. Volume: 44 5, May 1996, pp. 1288–1292.
f
–ν) gives good results in terms of BER of the overall communication system. Also, there are
Decision Feedback Equalizer for StarCore™-Based DSPs, Rev. 1
f
–1. In such systems the
Conclusion
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