CY22395 Cypress Semiconductor, CY22395 Datasheet - Page 13

• Manufacturer Part Number: CY22395
• Description: (CY22393 / CY22394 / CY22395) Three-PLL Serial-Programmable Flash-Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07186 Rev. *B
3.3V Switching Characteristics
2.5V Switching Characteristics
Switching Waveforms
Notes:
1/t
t
t
t
t
t
v
t
t
1/t
t
t
t
All Outputs, Duty Cycle and Rise/Fall Time
6. Guaranteed to meet 20%–80% output thresholds, duty cycle, and crossing point specifications.
7. Reference Output duty cycle depends on XTALIN duty cycle.
8. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
2
3
4
5
6
8
9
2_2.5
3_2.5
4_2.5
7
Parameter
Parameter
1
1_2.5
OUTPUT
Output Frequency
Output Duty Cycle
Rising Edge Slew Rate
Falling Edge Slew Rate
Output Frequency
Output Duty Cycle
Rising Edge Slew
Rate
Falling Edge Slew
Rate
Output three-state
Timing
Clock Jitter
P+/P– Crossing Point
P+/P– Jitter
Lock Time
[4]
[4]
Description
Description
[4]
t
3
[4]
[4, 8]
[4, 8]
[4, 6]
[4, 7]
[4, 6]
[4, 7]
[4]
[4]
[4]
(CY22395 only)
t
Clock output limit, CMOS, Commercial
Clock output limit, CMOS, Industrial
Clock output limit, PECL, Commercial (CY22394
only)
Clock output limit, PECL, Industrial (CY22394
only)
Duty cycle for outputs, defined as t
Fout<100 MHz, divider>=2,
measured at V
Duty cycle for outputs, defined as t
Fout>100 MHz or divider = 1,
measured at V
Output clock rise time, 20% to 80% of V
Output clock fall time, 20% to 80% of V
Time for output to enter or leave three-state
mode after SHUTDOWN/OE switches
Peak-to-peak period jitter, CLK outputs
measured at V
Crossing point referenced to Vdd/2, balanced
resistor network (CY22394 only)
Peak-to-peak period jitter, P+/P– outputs
measured at crossing point (CY22394 only)
PLL Lock Time from Power-up
2
Clock output limit, LVCMOS
Duty cycle for outputs, defined as t
measured at LV
Output clock rise time, 20% to 80% of LV
Output clock fall time, 20% to 80% of LV
t
1
DD
DD
DD
[5]
t
Conditions
4
DD
/2
/2
/2
Conditions
/2
2
2
2
³ t
³ t
÷ t
1
1
DD
1
,
,
DD
DD
DD
Min.
40%
0.5
0.5
Min.
45%
40%
0.75
0.75
–0.2
100
125
50%
Typ.
1.0
1.0
Typ.
50%
50%
150
400
200
1.4
1.4
1.0
0
CY22393
CY22394
CY22395
Max.
60%
Max.
133
55%
60%
Page 13 of 19
166
400
375
300
200
0.2
3
MHz
MHz
MHz
MHz
V/ns
V/ns
MHz
Unit
Unit
V/ns
V/ns
ms
ns
ps
ps
V