CY22395 Cypress Semiconductor, CY22395 Datasheet - Page 8

• Manufacturer Part Number: CY22395
• Description: (CY22393 / CY22394 / CY22395) Three-PLL Serial-Programmable Flash-Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07186 Rev. *B
Serial Programming Interface (SPI) Protocol
and Timing
The CY22393,CY22394 and CY22395 utilizes a 2-serial-wire
interface SDAT and SCLK that operates up to 400 kbits/sec in
Read or Write mode. The basic Write serial format is as
follows:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is
illustrated in Figure 2.
Default Startup Condition for the CY22393/94/95
The default (programmed) condition of each device is
generally set by the distributor, who will program the device
using a customer-specified JEDEC file produced by
CyClocksRT, Cypress’s proprietary development software.
Parts shipped by the factory are blank and unprogrammed. In
this condition, all bits are set to 0, all outputs are three-stated,
and the crystal oscillator circuit is active.
While users can develop their own subroutine to program any
or all of the individual registers as described in the following
pages, it may be easier to simply use CyClocksRT to produce
the required register setting file.
Device Address
The device address is a 7-bit value that is configured during
Field Programming. By programming different device
addresses, two or more parts can be connected to the serial
interface and be independently controlled. The device address
is combined with a read/write bit as the LSB and is sent after
each start bit.
The default serial interface address is 69H, but should there
be a conflict with any other devices in your system, this can
also be changed using CyClocksRT.
Data Valid
Data is valid when the clock is HIGH, and may only be transi-
tioned when the clock is LOW as illustrated in Figure 3.
Addr
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
(1,0)
100
101
110
111
S2
DivSel
DivSel
DivSel
DivSel
b7
PLL1_En
PLL1_En
PLL1_En
PLL1_En
b6
b5
PLL1_LF[2:0]
PLL1_LF[2:0]
PLL1_LF[2:0]
PLL1_LF[2:0]
b4
PLL1_Q[7:0]
PLL1_Q[7:0]
PLL1_Q[7:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_P[7:0]
PLL1_P[7:0]
PLL1_P[7:0]
Data Frame
Every new data frame is indicated by a start and stop
sequence, as illustrated in Figure 4.
Start Sequence - Start Frame is indicated by SDAT going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W
bit, followed by register address (eight bits) and register data
(eight bits).
Stop Sequence - Stop Frame is indicated by SDAT going HIGH
when SCLK is HIGH. A Stop Frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Acknowledge Pulse
During Write Mode the CY22393,CY22394 and CY22395 will
respond with an Acknowledge pulse after every eight bits. This
is accomplished by pulling the SDAT line LOW during the N*9
clock cycle as illustrated in Figure 5. (N = the number of bytes
transmitted). During Read Mode the acknowledge pulse after
the data packet is sent is generated by the master.
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is
followed by an acknowledge bit from the slave (ack = 0/LOW).
The next eight bits must contain the data word intended for
storage. After the data word is received, the slave responds
with another acknowledge bit (ack = 0/LOW), and the master
must end the write sequence with a STOP condition.
Writing Multiple Bytes
In order to write more than one byte at a time, the master does
not end the write sequence with a stop condition. Instead, the
master can send multiple contiguous bytes of data to be
stored. After each byte, the slave responds with an
acknowledge bit, just like after the first byte, and will accept
data until the acknowledge bit is responded to by the STOP
condition. When receiving multiple bytes, the CY22393,
CY22394, and CY22395 internally increments the register
address.
b3
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
b2
b1
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
CY22393
CY22394
CY22395
Page 8 of 19
b0
th