CY22395 Cypress Semiconductor, CY22395 Datasheet - Page 6

• Manufacturer Part Number: CY22395
• Description: (CY22393 / CY22394 / CY22395) Three-PLL Serial-Programmable Flash-Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07186 Rev. *B
Memory Bitmap Definitions
Clk{A–D}_Div[6:0]
Each of the four main output clocks (CLKA–CLKD) features a
7-bit linear output divider. Any divider setting may be used
between 1 and 127 by programming the value of the desired
divider into this register. Odd divide values are automatically
duty-cycle corrected. Setting a divide value of zero powers
down the divider and forces the output to a three-state
condition.
CLKA and CLKB have two divider registers, selected by the
DivSel bit (which in turn is selected by S2, S1, and S0). This
allows dynamic changing of the output divider value. For the
CY22394 device, ClkD_Div = 000001.
ClkE_Div[1:0]
CLKE has a simpler divider.
ClkE_Div = 01.
Clk*_FS[2:0]
Each of the four main output clocks (CLKA–CLKD) has a
three-bit code that determines the clock sources for the output
divider. The available clock sources are: Reference, PLL1,
PLL2, and PLL3. Each PLL provides both positive and
negative phased outputs, for a total of seven clock sources.
Note that the phase is a relative measure of the PLL output
phases. No absolute phase relation exists at the outputs.
Xbuf_OE
This bit enables the XBUF output when HIGH. For the
CY22395, Xbuf_OE = 0.
PdnEn
This bit selects the function of the SHUTDOWN/OE pin. When
this bit is HIGH, the pin is an active LOW shutdown control.
When this bit is LOW, this pin is an active HIGH output enable
control.
ClkE_Div[1:0]
Clk*_FS[2:0]
000
001
010
100
101
011
110
111
00
01
10
11
Reference Clock
Reserved
PLL1 0° Phase
PLL1 180° Phase
PLL2 0° Phase
PLL2 180° Phase
PLL3 0° Phase
PLL3 180° Phase
PLL1 0° Phase/4
PLL1 0° Phase/2
PLL1 0° Phase/3
For the CY22394, set
Clock Source
ClkE Output
Off
Clk*_ACAdj[1:0]
These bits modify the output predrivers, changing the duty
cycle through the pads. These are nominally set to 01, with a
higher value shifting the duty cycle higher. The performance of
the nominal setting is guaranteed.
Clk*_DCAdj[1:0]
These bits modify the DC drive of the outputs. The perfor-
mance of the nominal setting is guaranteed.
PLL*_Q[7:0]
PLL*_P[9:0]
PLL*_P0
These are the 8-bit Q value and 11-bit P values that determine
the PLL frequency. The formula is:
PLL*_LF[2:0]
These bits adjust the loop filter to optimize the stability of the
PLL. The following table can be used to guarantee stability.
However, CyClocksRT uses a more complicated algorithm to
set the loop filter for enhanced jitter performance. It is recom-
mended to use the Print Preview function in CyClocksRT to
determine the charge pump settings for optimal jitter perfor-
mance.
PLL*_En
This bit enables the PLL when HIGH. If PLL2 or PLL3 are not
enabled, then any output selecting the disabled PLL must
have a divider setting of zero (off). Since the PLL1_En bit is
dynamic, internal logic automatically turns off dependent
outputs when PLL1_En goes LOW.
DivSel
This bit controls which register is used for the CLKA and CLKB
dividers.
PLL*_LF[2:0]
Clk*_DCAdj[1:0]
000
001
010
100
011
00
01
10
11
P
T
F
PLL
=
(
Q
–30% of nominal
Nominal
+15% of nominal
+50% of nominal
2
=
t
P
×
1044
F
=
T
232
627
835
(
16
REF
P
Min
Q
Output Drive Strength
+
+
3
×
2
)


)
------ -
Q
P
+
T
T
PO


CY22393
CY22394
CY22395
P
Page 6 of 19
1043
1600
T
231
626
834
Max