CY28322-2 Cypress, CY28322-2 Datasheet
CY28322-2
Related parts for CY28322-2
CY28322-2 Summary of contents
Page 1
... Stop Clock PCI0:5 Control VDD_3V66 3V66_0:1 3V66_2:4/ 66BUFF0:2 3V66_5/ 66IN VDD_48MHz USB (48MHz) DOT (48MHz) VCH_CLK/ 3V66_1 • 3901 North First Street • CY28322-2 Differential CPU Outputs Benefits Pin Configurations TSSOP Top View VDD_REF XTAL_IN 1 48 REF0 XTAL_OUT 47 2 GND_REF 46 S1 ...
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... MHz Input 66IN/2 66IN 66 MHz Input 66IN/2 66 MHz 66 MHz 33 MHz 66 MHz 66 MHz 33 MHz TCLK/4 TCLK/4 TCLK/8 Reserved Reserved Reserved CY28322-2 Pin Description USB/DOT (MHz) REF0(MHz) (MHz) 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz TCLK TCLK/2 Reserved ...
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... SMBus interface is provided according to SMBus specification. Through the Serial Data Interface, various device functions such as individual clock output buffers, can be individually enabled or disabled. CY28322-2 supports both block read and block write operations. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional ...
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... Reserved Pin Description N/A PCI5 Output Enable 1 = Enabled Disabled PCI4 Output Enable 1 = Enabled Disabled PCI3 Output Enable 1 = Enabled Disabled PCI2Output Enable 1 = Enabled Disabled PCI1 Output Enable 1 = Enabled Disabled PCI0 Output Enable 1 = Enabled Disabled Write to”0” CY28322-2 Power-on Type Default R R N/A R/W N/A R N/A ...
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... Allow control of PCI_F0 with assertion of PCI_STOP Free running Stopped with PCI_STOP# PCI_F2 Output Enable PCI_F1Output Enable PCI_F0 Output Enable Pin Description Pin Description N/A N/A Tpd 66IN to 66BUFF propagation delay control DOT edge rate control USB edge rate control Description CY28322-2 Power-on Type Default R/W 1 R/W 1 R/W 0 R/W 0 R/W ...
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... Byte 6: Vendor ID (continued) Bit Bit 4 Revision Code Bit 0 Bit 3 Vendor ID Bit 3 Bit 2 Vendor ID Bit 2 Bit 1 Vendor ID Bit 1 Bit 0 Vendor ID Bit 0 Document #: 38-07145 Rev. *B PRELIMINARY Description CY28322-2 Power-on Type Default Page ...
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... Configuration OH REF, DOT, USB 3V66, DOT, PCI REF, DOT, USB 3V66, PCI Three-state VDD_CORE/VDD3.3 = 3.465V and @ IREF = 2.32 mA (Byte1, Bit [ VDD_CORE/VDD3.3 = 3.465V and @ IREF = 5.0 mA (Byte1, Bit [ VDD_CORE/VDD3.3 = 3.465V (Byte1, Bit [ CY28322-2 Min. Max. 3.135 3.465 2.85 3.465 22 ...
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... Measured differential waveform from –0.35V to +0.35V Measured at Crossover Measured at Crossover t Measured with test loads Measured with test loads Measured with test loads Measured with test loads = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V CY28322-2 Test Conditions Min. 45 0.5 1.0 1 – – ...
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... Definition and Application of PWRGD# Signal VRM8.5 PWRGD# CLOCK S0 GENERATOR S1 Document #: 38-07145 Rev. *B PRELIMINARY Vtt PWRGD# BSEL0 3.3V 3.3V NPN 10K 10K CY28322-2 CPU BSEL1 3.3V 10K GMCH 10K Page ...
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... Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock Skew 3V66 3V66 t 5 Document #: 38-07145 Rev. *B PRELIMINARY CY28322-2 Page ...
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... Switching Waveforms (continued) PCI-PCI Clock Skew PCI PCI t 6 3V66-PCI Clock Skew 3V66 PCI t 7 CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK Document #: 38-07145 Rev. *B PRELIMINARY CY28322-2 Page ...
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... CPU# 3V66 66IN USB REF Note: PCI_STOP# asserted LOW PWRDWN# Deassertion 66BUFF1/GMCH 66BUFF0,2 PCI PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 66IN USB REF Note: PCI_STOP# asserted LOW Document #: 38-07145 Rev. *B PRELIMINARY Power-down Rest of Generator 10-30 s min. 100-200 s max. <3 ms CY28322-2 UNDEF Page ...
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... Possible glitch while Clock VCC is coming up. Will be gone in 0.2–0.3 mS delay. Wait for 0.2 -- 0.3 ms delay PWRGD# State 1 State 2 Figure 2. CPU Power BEFORE Clock Power Sample Wait for BSELS PWRGD# State 2 Figure 3. CPU Power AFTER Clock Power CY28322-2 Sample BSELS State State Page ...
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... *Option Core 0.005 0 =VIA to respective supply plane layer CY28322 VDDQ3 *Option Page ...
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... Test Node 30 pF Ordering Information Ordering Code CY28322ZC-2 Document #: 38-07145 Rev. *B PRELIMINARY 3, 7, 16, 27, 32, 41 11, 15, 28, 40, 44, 48 CY28322-2 Ref,USB Outputs 20 pF PCI,3V66 Outputs 1.0V Amplitude Package Type 48-pin TSSOP CY28322-2 1.0V Test Load 475 Test CPU Nodes 33 OUTPUTS 2 pF 63.4 63.4 Operating Range Commercial ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 48-pin Thin Shrink Small Outline Package CY28322-2 Page ...
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... Document Title: CY28322-2 133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Document Number: 38-07145 Issue REV. ECN NO. Date ** 112664 03/01/02 *A 114703 04/29/02 *B 122796 12/14/02 Document #: 38-07145 Rev. *B PRELIMINARY Orig. of Change IKA New Data Sheet INA Corrections on some PIN numbers. RBI Add Power up Requirements to Operating Conditions Information ...