CY28322-2 Cypress, CY28322-2 Datasheet - Page 5

• Manufacturer Part Number: CY28322-2
• Description: 133 Mhz Spread Spectrum Clock Synthesizer with Differential CPU Outputs
• Manufacturer: Cypress

Document #: 38-07145 Rev. *B
Data Byte 3
Data Byte 4
Data Byte 5
Byte 6: Vendor ID
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit
Bit
Bit
Pin#
29
31
20
19
18
17
–
–
Bit
TBD
TBD
3V66_0
3V66_1/VCH
66IN/3V66_5
66BUFF2
66BUFF1
66BUFF0
Pin#
Pin#
34
35
6
5
4
6
5
4
Name
DOT
DOT
USB
PCI_F2
PCI_F1
PCI_F0
PCI_F2
PCI_F1
PCI_F0
N/A
N/A
66BUFF [2:0]
66BUFF [2:0]
DOT
USB
USB
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
N/A
N/A
1 = Enabled; 0 = Disabled
1 = Enabled; 0 = Disabled
1 = Enable; 0 = Disable
Note. This bit should be used when pin 24 is configured as 3v66_5 output.
Do not clear this bit when pin 24 is configured as 66IN input.
66-MHz Buffered 2 Output Enable
1 = Enabled; 0 = Disabled
66-MHz Buffered 1 Output Enable
1 = Enabled; 0 = Disabled
66-MHz Buffered 0 Output Enable
1 = Enabled; 0 = Disabled
3V66_0 Output Enable
3V66_1/VCH Output Enable
3V66_5 Output Enable
Name
Name
Description
DOT 48-MHz Output Enable
USB 48-MHz Output Enable
Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
PCI_F2 Output Enable
PCI_F1Output Enable
PCI_F0 Output Enable
N/A
N/A
Tpd 66IN to 66BUFF propagation delay control
DOT edge rate control
USB edge rate control
PRELIMINARY
Pin Description
Pin Description
Pin Description
Type
R
R
R
Power-on
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
CY28322-2
R
R
R
R
0
0
0
Page 5 of 17
Power-on
Power-on
Power-on
Default
Default
Default
1
1
0
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0