CY28322-2 Cypress, CY28322-2 Datasheet - Page 3

• Manufacturer Part Number: CY28322-2
• Description: 133 Mhz Spread Spectrum Clock Synthesizer with Differential CPU Outputs
• Manufacturer: Cypress

Document #: 38-07145 Rev. *B
Clock Driver Impedances
Clock Enable Configuration
Serial Data Interface (SMBus)
To enhance the flexibility and function of the clock synthesizer,
a two signal SMBus interface is provided according to SMBus
specification. Through the Serial Data Interface, various
device functions such as individual clock output buffers, can
be individually enabled or disabled. CY28322-2 supports both
block read and block write operations.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte, (most significant bit first) with the
CPU, CPU#
REF
PCI, 3V66, 66BUFF
USB
DOT
Start
1 bit
PWR_DWN# CPU_STOP# PCI_STOP#
Bit
0
1
1
1
1
Slave Address
1 1 0 1 0 0 1 0
Buffer
7 bits
From Master to Slave
From Slave to Master
X
0
0
1
1
R/W
0/1
1
3.135–3.465
3.135–3.465
3.135–3.465
3.135–3.465
V
DD
A
1
Range
0 0 0 0 0 0 0 0
Command
X
0
1
0
1
Code
8 bits
Figure 1. An Example of a Block Write
IREF*2
IREF*2
IREF*2
Buffer Type
CPU
ON
ON
PRELIMINARY
Type X1
Type 3A
Type 3B
Type 3
Type 5
A Byte Count =
1
FLOAT
FLOAT
FLOAT
CPU#
ON
ON
8 bits
N
ability to stop after any complete byte has been transferred.
Indexed bytes are not allowed.
A block write begins with a slave address and a WRITE
condition. The R/W bit is used by the SMBus controller as a
data direction bit. A zero indicates a WRITE condition to the
clock device. The slave receiver address is 11010010 (D2h).
A command code of 0000 0000 (00h) and the byte count bytes
are required for any transfer. After the command code, the
core logic issues a byte count which describes number of
additional bytes required for the transfer, not including the
command code and byte count bytes. For example, if the host
has 20 data bytes to send, the first byte would be the number
20 (14h), followed by the 20 bytes of data. The byte count byte
is required to be a minimum of 1 byte and a maximum of 32
bytes It may not be 0. Figure 1 shows an example of a block
write.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
3V66
LOW
ON
ON
ON
ON
A Data Byte 0 A
1
Min.
20
12
12
12
66BUFF
8 bits
LOW
ON
ON
ON
ON
PCI_F
LOW
1
ON
ON
ON
ON
Impedance
Typ.
. . .
50
40
30
30
30
LOW
OFF
OFF
PCI
ON
ON
USB/DOT
Data Byte N-1 A Stop
LOW
ON
ON
ON
ON
8 bits
CY28322-2
Max.
Page 3 of 17
60
55
55
55
VCOS/
OSC
OFF
1 1 bit
ON
ON
ON
ON
Bit