AN2148 Motorola / Freescale Semiconductor, AN2148 Datasheet - Page 14

• Manufacturer Part Number: AN2148
• Description: Design Considerations for Interfacing SDRAM with MC68VZ328
• Manufacturer: Motorola / Freescale Semiconductor

SDRAM Control Registers
Figure 7 depicts the internal structure of the logic. Two multiplexors will derive the bank address based on
the setting of the SDCTRL register bits BNKADDH[1:0] and BNKADDL[1:0]. The controller supports 4
banks, therefore there are two lines of bank address. However, bnkaddH and bnkaddL signals are used by
internal bank register and page hit detection logic to track whether the current access is on the same page of
previous access in the same bank. Each individual bank has its own logic.
For 2 bank device, only one mux from the pair is used. The other mux is programmed to ’11’ (outputs ’0’).
Therefore only two possible bank registers are present apparently. For 4 bank device, both two mux are
used to form 2 line bank address (bnkaddH and bnkaddL) therefore all four bank registers are used. Users
may want to treat multibank device as a one bank device. In this case the user should program both
BNKADDH and BNKADDL to '11' (output ’0’). The logic will see only one bank register apparently.
Table 7-9 in the VZ user manual provides information on how to set these bits.
Continuous Page Mode or CPM bit in the SDCTRL register can also be enabled at this time. The CPM
feature can accelerate SDRAM read/write cycles by eliminating unneeded precharge cycles. With CPM
enabled, access to a page for the first time will generate a page-miss flag which will send a precharge then
a read/write command. Subsequent access to the page will generate a page-hit flag which is followed
immediately by the read/write command. Setting CPM is also another method in circumventing the
multibank issue mentioned above.
Before the SDRAM is fully operational, its has to go through an initialization sequence.
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Initiate an all bank precharge with the IP bit
First Access
-Precharged
-Row Activated
-Read Command
1
It is currently recommended that all BNKADDH/L bits be set to ’1’ for
SDRAM to appear as one single bank. This is due to a silicon bug
documented in the VZ design. Multibank setting under CAS latency 2 can
cause the DragonBall VZ to stop responding to commands if the LCD and
the CPU are accessing seperate banks.The erratum is listed in errata
document which can be downloaded from www.motorola.com/dragonball
IP = 1, RE = 0, MR = 0
Design Considerations for Interfacing SDRAM with MC68VZ328
64Mbit SDRAM
NOTE: VZ Silicon Bug in SDRAM Bank Handling
Figure 8. Continuous Page Mode
Second Access
-Read Command
2
Pre-Publication Draft
Page-Hit!
1 Page
First Access
-Precharged
-Row Activated
-Read Command
1
64Mbit SDRAM
Second Access
-Precharge
-Row Activate
-Read Command
2
Page-Miss!
1 Page