AN2148 Motorola / Freescale Semiconductor, AN2148 Datasheet - Page 5

• Manufacturer Part Number: AN2148
• Description: Design Considerations for Interfacing SDRAM with MC68VZ328
• Manufacturer: Motorola / Freescale Semiconductor

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This application note provides information for users who are preparing to use Synchronous
DRAM (SDRAM) with the MC68VZ328 (VZ). This document is a pre-publication draft.
The following issues are covered in this application note:
It is assumed that users have a basic understanding of the DragonBall processors and SDRAM operation.
A large amount of abbreviations are used throughout this application note. Please refer to MC68VZ328
User’s Manual (order number MC68VZ328UM/D) for details if needed.
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Unless otherwise specified, the following terms and abbreviation are as defined below.
1. Physical interface between SDRAM and MC68VZ328.
2. Relevant control registers for SDRAM operation in the MC68VZ328 memory controller.
3. SDRAM Initialization sequences.
4. SDRAM Power control features.
5. SDRAM Logic Analyser Captures.
CPU
LCDC
*UDS
*SDCS0
*SDCAS
*SDRAS
*SDWE
SDCLK
SDCE
SDA10
Terms
Introduction
Terminology
The 68K core in the DragonBall Processor.
LCD Controller module in the DragonBall Processor.
Upper Data Strob signal from the 68K core, this is muxed with Port K3 (PK3/UDS)
SDRAM Chip Select 0, muxed with Port B4 (PB4/CSD0/CAS0/SDCS0)
SDRAM CAS Signal, muxed with Port B3 (PB3/CSC1/RAS1/SDCAS)
SDRAM RAS Signal, muxed with Port B2 (PB2/CSC0/RAS0/SDRAS)
SDRAM Write Enable Signal, muxed with Port B1 (PB1/CSB1/SDWE)
SDRAM Clock Signal, muxed with Port M0 (PM0/SDCLK)
SDRAM Clock Enable Signal, muxed with Port M1 (PM1/SDCE)
SDRAM Address Line 10 Signal, muxed with Port M4 (PM4/SDA10)
Table 1. Terminology
Pre-Publication Draft
Introduction
Description
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