CY28347 Cypress Semiconductor, CY28347 Datasheet - Page 15

• Manufacturer Part Number: CY28347
• Description: Universal Single-chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07352 Rev. *C
CPU_STP# Assertion (P4 Mode)
When CPU_STP# pin is asserted, all CPU outputs will be
stopped after being sampled by two rising CPUC clock edges.
The final state of the stopped CPU signal is CPUT = HIGH and
CPUC = LOW. There is no change to the output drive current
Table 12. CPU_STP# Functionality
CPU_STP#
CPU_STP#
CPU_STP#
CPUCS_C
CPUCS_T
1
0
CPUC
CPUC
CPUT
CPUT
Iref*Mult
CPU#4
Normal
Figure 8. CPU_STP# Deassertion Waveform (P4 Mode)
Figure 7. CPU_STP# Assertion Waveform (P4 Mode)
Normal
Float
CPU
values during the stopped state. The CPUT is driven HIGH
with a current value equal to (Mult 0 “select”) x (Iref), and the
CPUC signal will not be driven. Due to external pulldown
circuitry CPUC will be LOW during this stopped state.
CPU_STP# Deassertion (P4 Mode)
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CY28347
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