AN2184 Freescale Semiconductor / Motorola, AN2184 Datasheet - Page 27

• Manufacturer Part Number: AN2184
• Description: MCF5272 Interrupt Service Routine for the Physical Layer Interface Controller
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Appendix A Software Configuration
# Nothing on CS3 at 0x00000000
# write -l 0x10000058=0x00000000
# write -l 0x1000005C=0x00000000
# CS7 from address 0x00000000 4M byte SDRAM
write -l 0x10000078 = 0x00000701
write -l 0x1000007C = 0xFFC0007c
# setup SDRAM Timing and Control Registers SDCTR then SDCCR
write -l 0x10000184 = 0x0000f415
write -l 0x10000180 = 0x00004211
# rem initialize SDRAM with a write
write -r 0x00040000=0x55555555 # STARTS SDRAM controller
Part VIII Appendix A
This appendix deals with an example of program that has been used to evaluate the MCF5272.
Scope of the program:
The purpose of that program was not to productize the MCF5272, but to simply evaluate the silicon. This is
the reason why the internal architecture might not be optimized to the fullest. Some knowledge of
Motorola ISDN products is required, in order to fully activate and send data over the data link. For more
information, the user must refer to the MC145572 and MC145574 User’s Manuals.
Once the hardware has been correctly set up (see Figure 20), the NT-configured MC145574 chip activates
the (NR2 to 0x1) down to the TE-configured MC145574 device. When the link is up and running (NR1 to
0x9), the TE must have the B1 and B2 channels on (NR5 to 0xC). Once connected to the NT-configured T
chip, the bit error rate tester (HP 1645A) sends data from the NT device through the link down to the TE
device. The purpose of MCF5272 is to capture the received data and to perform a loopback in the ColdFire
core via the interrupt service routine. The possible loopbacks that can be tested are all combinations of B
channels or D channel by itself. Due to the internal architecture and the special processing of the D
channel, the 2B+D loopback cannot be performed. The entire loopback process runs in the ISR. The flow
diagram of the program (for both IDL and GCI modes, except that there is no aperiodic interrupt in IDL
mode) is as follows:
MCF5272 Interrupt Service Routine
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