AN2184 Freescale Semiconductor / Motorola, AN2184 Datasheet - Page 9

• Manufacturer Part Number: AN2184
• Description: MCF5272 Interrupt Service Routine for the Physical Layer Interface Controller
• Manufacturer: Freescale Semiconductor / Motorola

4.3 Command Indicate Registers
This section describes receive and transmit command registers.
4.3.1 Command Indicate Receive
The P n GCIR register is an 8-bit register containing the received C/I bits for one of each of the four ports on
the MCF5272. The register is shown in Figure 7 and described in Table 3.
4.3.2 Command Indicate Transmit
The P n GCIT registers are 8-bit registers containing the monitor channel bits to be transmitted for each of
the four ports on the MCF5272. The register is shown in Figure 8 and described in Table 4.
Bits
7–0
8
Name
Bits Name
7–5
3–0 C3–C0 C/I bits. These four bits are received on the GCI or SCIT channel 0. When a change in
4
M
R
Ready.
0 Default reset value.
1 Set by the CPU. Indicate to the monitor channel controller that a byte of data is ready for
Monitor channel data byte. Written by the CPU when a byte is ready for transmission.
—
F
transmission. Automatically cleared by the GCI controller when it generates a transmit
acknowledge (ACK bit in P
Reserved, should be cleared.
Full. This bit is set by the C/I channel controller to indicate to the CPU that new C/I
channel data has been received and is available for processing. It is automatically
cleared by a CPU read. The clearing of this bit by reading this register also clears the
aperiodic GCR interrupt.
the C/I data value is received in two successive frames, it is interpreted as being valid
and is passed on to the CPU via this register. A maskable interrupt is generated when
data is written into any of the four available positions.
Reset
Read
Field
Freescale Semiconductor, Inc.
Table 3. P n GCIR Register Field Descriptions
Table 2. P n GMT Register Field Descriptions
For More Information On This Product,
7
MCF5272 Interrupt Service Routine
Figure 7. P n GCIR Register
—
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n
GMTS register) or when the L bit is reset.
5
GCI/IDL and the MCF5272 Command Indicate Registers
0000_0000
F
4
Description
R/W
Description
C3
3
C2
2
C1
1
C0
0
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