CY28441 Cypress Semiconductor, CY28441 Datasheet - Page 12

• Manufacturer Part Number: CY28441
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07679 Rev. **
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t
Figure 10.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running.
Note:
1. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 55 and the other is SMBus byte6 bit 3. These two inputs are logically
OR’ed. If either the external pin or the internal SMBus register bit is set LOW then the stoppable PCI clocks will be stopped in a logic LOW state.
SRC 100MHz
SRC 100MHz
PCI_STP#
PCI_STP#
[1]
PCI_F
PCI_F
PCI
PCI
Figure 11. PCI_STP# Deassertion Waveform
Tsu
Tsu
Figure 10. PCI_STP# Assertion Waveform
Tdrive_SRC
SU
). (See
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level. (See Figure 11.)
CY28441
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