CY28441 Cypress Semiconductor, CY28441 Datasheet - Page 7

• Manufacturer Part Number: CY28441
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07679 Rev. **
Byte 6: Control Register 6 (continued)
Byte 7: Vendor ID
BYTE 8: CLKREQ Control Register
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit
Bit
Bit
1
6
5
4
3
2
0
Externally
Externally
Externally
selected
selected
selected
@Pup
@Pup
@Pup
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Reserved
CLKREQ#B
CLKREQ#B
CLKREQ#B
Reserved
CLKREQ#A
CLKREQ#A
CLKREQ#A
PCIF, SRC, PCI
Reserved
CPUT/C
CPUT/C
CPUT/C
Name
Name
Name
REF
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Hi-Z mode,
Reserved, Set = 0
REF Output Drive Strength
0 = 1X, 1 = 2X
SW PCI_STP Function
0=SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
FS_C Reflects the value of the FS_C pin sampled on power up
0 = FS_C was low during VTT_PWRGD# assertion
FS_B Reflects the value of the FS_B pin sampled on power up
0 = FS_B was low during VTT_PWRGD# assertion
FS_A Reflects the value of the FS_A pin sampled on power up
0 = FS_A was low during VTT_PWRGD# assertion
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Reserved
SRC[T/C]5 CLKREQ#B control
1 = SRC[T/C]5 stoppable by CLKREQ#B pin
0 = SRC[T/C]5 not controlled by CLKREQ#B pin
SRC[T/C]3 CLKREQ#B control
1 = SRC[T/C]3 stoppable by CLKREQ#B pin
0 = SRC[T/C]3 not controlled by CLKREQ#B pin
SRC[T/C]1 CLKREQ#B control
1 = SRC[T/C]1 stoppable by CLKREQ#B pin
0 = SRC[T/C]1 not controlled by CLKREQ#B pin
Reserved
SRC[T/C]4 CLKREQ#A control
1 = SRC[T/C]4 stoppable by CLKREQ#A pin
0 = SRC[T/C]4 not controlled by CLKREQ#A pin
SRC[T/C]2 CLKREQ#A control
1 = SRC[T/C]2 stoppable by CLKREQ#A pin
0 = SRC[T/C]2 not controlled by CLKREQ#A pin
SRC[T/C]0 CLKREQ#A control
1 = SRC[T/C]0 stoppable by CLKREQ#A pin
0 = SRC[T/C]0 not controlled by CLKREQ#A pin
Description
Description
Description
CY28441
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