CY2DP1510 Cypress Semiconductor, CY2DP1510 Datasheet - Page 12

• Manufacturer Part Number: CY2DP1510
• Description: 1:10 LVPECL Fanout Buffer
• Manufacturer: Cypress Semiconductor

Document History Page
Document Number: 001-55566 Rev. *G
Revision
Document Title: CY2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input
Document Number: 001-55566
*C
*D
*G
*A
*B
*E
*F
**
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3090938
ECN
Change
Orig. of
CXQ
CXQ
CXQ
CXQ
CXQ
CXQ
CXQ
CXQ
Submission
01/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”.
02/26/2010 Updated 32-Pin TQFP package diagram.
08/23/2010 Changed from 0.25 ps to 0.11 ps maximum additive jitter in “Features” on page
08/27/2010 Corrected Output Rise/Fall time diagram.
11/18/2010 Changed V
01/12/2011 Removed “Preliminary” status heading.
02/25/2011 Post to external web.
10/09/09
Date
New Datasheet.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page
1 and in t
Added t
Changed V
- 1.15V to V
Removed V
Changed V
- 1.38V to V
Added R
= 140 kΩ.
Added a measurement definition for C
page 4.
Added V
mV for DC - 150 MHz and min = 400 mV for 150 MHz to 1.5 GHz.
Changed letter case and some names of all the timing parameters in the AC
Electrical Specs table on page 5 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 5.
Added condition to t
that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in Figures
3, 4, 5, 6 and 8, to be consistent with EROS.
1 and in t
Added description of EPAD to Table 1 pin definitions.
Added note 3 to describe I
Changed V
Removed reference to data distribution from “Functional Description”.
Changed R
Diagram and from 60 kΩ min / 140 kΩ max to 90 kΩ min / 210 kΩ max in the
DC Electrical Specs table.
Added max V
Changed t
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to
-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical
Specs table.
Added “Frequency range up to 1 GHz” condition to t
Updated package drawing to 001-54497 to reflect use of EPAD package.
Added Acronyms and Ordering Code Definition.
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test”
Removed R
Changed C
Changed PN
Removed pull-up/pull-down resistors from IN
Diagram.
PU
P
PP
JIT
JIT
spec in the DC Electrical Specs table on page 4. Min = 60 kΩ, Max
PD
spec to the Operating Conditions table on page 3.
OH
BB
BB
IN
P
IN
spec to the AC Electrical Specs table on page 5. V
OD
DD
DD
P
in the AC Electrical Specs table on page 5.
in the AC Electrical Specs table on page 6.
ADD
for differential inputs from 100 kΩ to 150 kΩ in the Logic Block
ID
max spec from 480 ps to 600 ps.
and V
spec for differential input clock pins IN
condition to “Measured at 10 MHz”.
max spec in the DC Electrical Specs table on page 4 from V
max from V
in the DC Electrical Specs table on page 4: minimum from V
- 1.20V; maximum from V
spec in the DC Electrical Specs table on page 4.
- 1.40V.
of 1.0V in DC Electrical Specs table.
specs for 100kHz, 10MHz, and 20MHz offsets.
R
OUT
and t
specs from 4.0V to “lesser of 4.0 or V
DD
Description of Change
IH
F
specs in the AC Electrical specs table on page 5
and I
- 1.26V to V
IL
specs.
IN
in the DC Electrical Specs table on
DD
DD
- 0.75V to V
- 1.16V in DC Electrical Specs.
x
/IN
x
# pins in
X
ODC
and IN
DD
spec.
CY2DP1510
Logic Block
- 0.70V.
X
DD
#.
PP
Page 12 of 13
+ 0.4”
min = 600
DD
DD
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