CY2DP1510 Cypress Semiconductor, CY2DP1510 Datasheet - Page 6

• Manufacturer Part Number: CY2DP1510
• Description: 1:10 LVPECL Fanout Buffer
• Manufacturer: Cypress Semiconductor

AC Electrical Specifications
(V
Document Number: 001-55566 Rev. *G
F
F
V
t
t
t
t
PN
t
t
Notes
PD
ODC
SK1
SK1 D
JIT
R
6. Refer to
7. Refer to
8. Refer to
9. Refer to
10. Refer to
11. Refer to
IN
OUT
PP
DD
,t
[7]
ADD
[10]
F
Parameter
[9]
[11]
[8]
= 3.3 V ± 5% or 2.5 V ± 5%; T
[9]
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
on page 7.
on page 7.
on page 7.
on page 8.
on page 8.
on page 8.
Input frequency
Output frequency
LVPECL differential output voltage peak
to peak, single ended. Terminated with
50 Ω to V
Propagation delay input pair to output
pair
Output duty cycle
Output-to-output skew
Device-to-device output skew
Additive RMS phase noise
156.25-MHz input
Rise/fall time < 150 ps (20% to 80%)
V
Additive RMS phase jitter (Random)
Output rise/fall time
ID
> 400 mV
DD
– 2.0
Description
A
= 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
[6]
F
Fout = DC to 150 MHz
Fout = >150 MHz to 1.5 GHz
Input rise/fall time < 1.5 ns
(20% to 80%)
50% duty cycle at input
Frequency range up to 1 GHz
Any output to any output, with
same load conditions at DUT
Any output to any output
between two or more devices.
Devices must have the same
input and have the same output
load.
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 1 MHz
Offset = 10 MHz
Offset = 20 MHz
156.25 MHz, 12 kHz to 20 MHz
offset; input rise/fall time <
150 ps (20% to 80%), V
400 mV
50% duty cycle at input,
20% to 80% of full swing
(V
Input rise/fall time < 1.5 ns
(20% to 80%)
OUT
OL
to V
= F
IN
OH
Condition
)
ID
>
Min
600
400
DC
DC
48
–
–
–
–
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY2DP1510
–120
–130
–140
–150
–154
–155
Max
0.11
600
150
300
1.5
1.5
52
40
–
–
Page 6 of 13
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
GHz
GHz
Unit
mV
mV
ps
ps
ps
ps
ps
%
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