AN2313 Freescale Semiconductor / Motorola, AN2313 Datasheet - Page 2

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AN2313

Manufacturer Part Number
AN2313
Description
Connecting an MSC8102 TDM to an MSC8101 Device
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Configuring the MSC8102 TDMs
2
2
Configuring the MSC8102 TDMs
SYNC
Data
Note: The TDM0TDATA and TDM0RDAT ports function as data links.
TDM0TSYN
TDM0RDAT
TDM0TCLK
TDM0TDAT
Figure 2 shows a timing diagram for the interface between the MSC8102 and MSC8101. The TDM
frame supports four 8-bit channels.
The overall steps in initializing an MSC8102 TDM are as follows:
1. Initialize the configuration registers to define the basic interface between the external device and the
2. Initialize the channel parameter registers to determine the channel type (A-law, µ− law, or transparent)
3. Initialize the control registers.
4. Clear the event registers (TDMxRER, TDMxTER).
5. Configure the external interface:
This section defines the register settings used to complete these steps. For the example presented here, the
MSC8102 TDM transfers data to MSC8101 via the TDM0TDAT port, and it receives data via
TDM0RDAT. The receiver and transmitter of TDM0 share sync and clock signals, and the sync signal is
generated by TDM0 of the MSC8102 device. The receive and transmit buffers of MSC8102 TDM0 are
located in the L1 memory of the SC140 core 0 (CORE0), and the buffer size is 128 bytes. All the data
buffers are contiguous in memory
MSC8102 TDM.
and the buffer location of each channel.
The channel parameter register values can change during TDM operation.
a. Set up the parallel I/O pins.
b. Enable the TDM.
Channel 0
Freescale Semiconductor, Inc.
Figure 2. MSC8102 to MSC8101 Interface
For More Information On This Product,
Bit 7
Bit 7
Go to: www.freescale.com
Channel 1
Bit 6
Bit 6
Four Channels
Bit 5
Bit 5
Channel 2
Bit 4
Bit 4
Bit 3
Bit 3
Channel 3
Bit 2
Bit 2
Channel 0
Bit 1
Bit 1
Bit 0
Bit 0

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