AN2313 Freescale Semiconductor / Motorola, AN2313 Datasheet - Page 3

• Manufacturer Part Number: AN2313
• Description: Connecting an MSC8102 TDM to an MSC8101 Device
• Manufacturer: Freescale Semiconductor / Motorola

The data buffers of a TDM channel can be located in the L1 memory of the SC140 cores and in M2
memory. The location of each data buffer is independent and is indicated in the Receive/Transmit
Channel Parameter Registers (RCPR_X). The data buffer size is identical for all receive channels
belonging to a TDM module and is indicated by the TDMx[8–31]:RDBS field. The transmit buffer size is
also identical for all the transmit channels belonging to a TDM module and is indicated by the
TDMxTDBS[8–31]:TDBS field. The receive data buffer base address is a function of the following:
• Receive Global Base Address. TDMxRGBA[16–31]:RGBA field.
TDM0GIR[28–31]:RTSAL] = 0x4
TDM0GIR[27]:CTS = 0x0
TDM0RIR[26–27]:RFSD = 0x0
TDM0RIR[28]:RSL = 0x0
TDM0RIR[29]:RDE = 0x0
TDM0RIR[30]:RFSE = 0x0
TDM0RIR[31]:RRDO = 0x0
TDMTTIR[26–27]:TFSD = 0x1
TDM0TIR[28]:TSL = 0x0
TDM0TIR[29]:TDE = 0x0
TDM0TIR[30]:TFSE = 0x0
TDM0TIR[31]:TRDO = 0x0
TDM0TIR[18]:TSO = 0x0
TDM0TIR[21]:SOE = 0x1
TDM0TIR[20]:SOL = 0x0
TDM0TIR[19]:TAO = 0x1
TDM0RFP[8–15]:RNCF = 0x03
TDM0RFP[21–23]:RCDBL = 0x1
TDM0RFP[26–29]:RCS = 0x7
TDM0RFP[30]:RT1 = 0x0
TDM0RFP[31]:RUBM = 0x0
Register Setting Summary:
Register Setting Summary
Freescale Semiconductor, Inc.
Table 2. TDM0 Frame Parameter Register (TDM0RFP/TDM0TFP) Settings
Bit Setting
Bit Setting
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Table 1. TDM0 Interface Register Settings
Four receive channels (four channels per data link).
Receive data buffer latency is 128 bits.
Receive channel size is 8 bits.
The receive frame is not a T1 frame but an E1 frame.
The receiver operates in regular mode.
TDM0RFP = 32x0007011c,TDM0TFP = 32x0007011c
Note: TDM0RFP is identical to TDM0TFP because the receive and transmitter
operate in shared mode.
The receive and transmit have a common clock and sync. The TDM receives
one data link (TDM0RDAT) and transmits one data link (TDM0TDAT).
TDM0 does not share signals with the other TDM modules
There is no clock delay between the first bit of the receive frame and the
synchronization signal.
TDM0TSYN is an active high signal (TDM0SYN is common for receive and
transmit).
The receive data signal (TDM0RDAT) samples at the falling edge of
TDM0TCLK.
The TDM0TSYN signal is sampled at the rising edge of TDM0TCLK.
The MSB bit is received first.
There is no clock delay between the first bit of the transmit frame and the
synchronization signal.
TDM0TSYN is an active high signal (TDM0SYN is common for receive and
transmit).
The transmit data signal (TDM0TDAT) drives out on the rising edge of
TDM0TCLK.
The TDM0TSYN signal is sampled on the rising edge of TDM0TCLK.
The MSB bit is transmitted first.
TDM0TSYN is an output
TDM0TSYN is driven out on the falling edge of the transmit clock.
The TDM0TSYN signal is active during one bit transmission.
Data is always transmitted out.
TDM0GIR = 0x00000004, TDM0RIR = 32x00010004,
TDM0TIR = 32x00012410
Description
Description
Configuring the MSC8102 TDMs
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