AN2313 Freescale Semiconductor / Motorola, AN2313 Datasheet - Page 5

• Manufacturer Part Number: AN2313
• Description: Connecting an MSC8102 TDM to an MSC8101 Device
• Manufacturer: Freescale Semiconductor / Motorola

Before activating the TDM, you must enable the TDM0 interrupts by setting the TDM0RIER and
TDM0TIER registers to a value of 0xF. Also, you must clear the event registers TDM0RER and
TDM0TER by writing a value of 0xF to these registers.
TDM0TCPR2 = 0x80000300
TDM0TCPR3 = 0x80000380
Note: All the receive and transmit channels are active and transparent.
TDM0TDBFT[8–31]:TDBFT =
0x000038
TDM0TDBFT[8–31]:TDBFT =
0x000078
TDM0RDBFT[8–31]:RDBFT =
0x000038
TDM0RDBFT[8–31]:RDBFT] =
0x000078
PSOR = 32 × 07B00000
PODR = 32 × 0
PDIR = 32 × 0
PAR = 32 × 07F00000
Register Setting Summary:
TDM0RCR = 0x00000001
TDM0TCR = 0x00000001
Register Setting
Table 4. Receive/Transmit Channel Parameter Register Settings (Continued)
Freescale Semiconductor, Inc.
Register Setting
Bit Setting
Bit Setting
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Table 7. TDM0 Activation Register Settings
Table 5. Threshold Register Settings
Table 6. Parallel I/O Port Registers
The transmit data buffer of channel 2 is located at an offset of 768 bytes (refer
to the TDMxTGBA[16–31]:TGBA field). The address of transmit channel 2 is
0x2080300 (local memory address space).
The transmit data buffer of channel 3 is located at an offset of 896 bytes (refer
to the TDMxTGBA[16–31]:TGBA field). The address of transmit channel 3 is
0x2080380 (local memory address space).
The transmit first threshold interrupt is generated when the first half of the
data buffer is empty.
The transmit second threshold interrupt is generated when the second half of
the data buffers is empty.
The receive first threshold interrupt is generated when the first half of the data
buffer is full.
The receive second threshold interrupt is generated when the second half of
the data buffer is full.
TDM0RDBFT = 0x00000038,TDM0RDBST = 0x00000078,
TDM0TDBFT = 0x00000038,TDM0TDBST = 0x00000078
The TDM0TSYN, TDM0TDAT, TDM0TDAT, TDM0RDAT, and TDM0RSYN
ports are dedicated peripheral ports (option 2).
All the I/O ports are actively driven as outputs.
All the I/O ports counteract as inputs (the TDM determines the direction of the
port).
The TDM0TSYN, TDM0TDAT, TDM0TDAT, TDM0RDAT, TDM0RSYN, and
TDM0TCLK ports are dedicated peripheral ports.
Enable the TDM0 receiver
Enable the TDM0 transmitter
Description
Description
Description
Description
Configuring the MSC8102 TDMs
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