AN2400 Freescale Semiconductor / Motorola, AN2400 Datasheet - Page 20

• Manufacturer Part Number: AN2400
• Description: HCS12 NVM Guidelines
• Manufacturer: Freescale Semiconductor / Motorola

AN2400/D
Non-Paged Flash
Memory
Vector Table
Interrupt Service
Routines
20
NOTE:
$30-$3F correspond to the PPAGE register content.
Support for the paging mechanism is built into the HCS12 instruction set, with
the CALL and RTC instructions. The CALL instruction is like the JSR instruction
(jump to subroutine), but the CALL instruction automatically handles the
PPAGE register to transfer control to a subroutine in paged memory. The CALL
instruction requires one more byte of memory and three extra clock cycles to
execute than the JSR instruction. The CALL instruction need only be used
when a subroutine in a different page than the one currently selected is to be
called. Modern compilers for the HCS12, such as produced by Metrowerks, are
capable of determining whether a CALL or JSR instruction needs to be used
and can also arrange routines in memory to minimise the use of the CALL
instruction. The extra byte required for a CALL instruction is therefore only used
when required, offering enhanced code density over 24-bit instruction sets.
The RTC instruction is the equivalent to the RTS instruction, but restores the
PPAGE register to its value prior to the previous CALL instruction. The RTC
instruction requires one byte of memory, like the RTS instruction, but two extra
clock cycles to execute.
On HCS12 microcontrollers that employ flash memory paging, there are two
regions of addresses that access fixed regions of flash memory. These regions
are $4000 to $7FFF and $C000 to $FFFF. Each of these regions corresponds
to a fixed page, usually the two highest numbered pages. These pages may
also be accessed through the page window, although this is not normally done.
Because these fixed pages are permanently present in the memory map, they
are used to store certain items that must be accessible at all times and cannot
be stored in paged memory.
In order to service an interrupt or restart after a reset, the CPU must fetch the
address of the interrupt service routine (ISR) or the reset address. These
addresses are called vectors because they redirect the CPU to the appropriate
place to start executing code. The list of ISR addresses is called the Interrupt
Vector Table and this table also includes the reset vectors. The address of the
vector table is fixed in the design of the microcontroller and is located at
addresses $FF80 to $FFFF. As an interrupt or reset is by nature an
asynchronous event the vector table must be permanently accessible, hence
the table is stored at a non-paged address.
An interrupt service routine (ISR) contains code that is executed in order to
process an interrupt. The CPU obtains the address of the appropriate ISR from
the Interrupt Vector Table. As an interrupt is by nature an asynchronous event
each ISR must be permanently accessible and located in non-paged memory.
It is acceptable for an ISR to call subroutines that are located in paged memory,
if the time delay incurred by the page switch is acceptable.
Freescale Semiconductor, Inc.
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HCS12 NVM Guidelines
MOTOROLA