AN2505 Freescale Semiconductor / Motorola, AN2505 Datasheet - Page 7

• Manufacturer Part Number: AN2505
• Description: MSC8102 Asynchronous DSI Throughput
• Manufacturer: Freescale Semiconductor / Motorola

The DSI asynchronous read transaction, which is programmed into the MSC8101 UPM memory controller as a
single read, requires 5 cycles with a system bus clock of 66 MHz. The throughput is calculated by adding the
cycles of the UPM and synchronization of the
system bus operates at 66 MHz, the cycle time is 15.15 ns. If we assume 5 cycles for the UPM read and 4 cycles for
the
behavior for a MSC8102 DSI read transaction on the MSC8102ADS. Table 2 shows the distinction between the
theoretical throughput based on the timings versus the theoretical throughput based on the host programming and
synchronization.
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The actual throughput measurements for the DSI asynchronous mode greatly depend on such conditions as DSI
data bus width, mode of operation, load on the MSC8102 local bus, load on the MSC8101 system bus, single or
host DMA accesses, and local bus frequency.
4.1 Asynchronous Throughput Measurements
The conditions, modes and register settings used to obtain the DSI throughput performance measurements
discussed in this section are as follows:
Freescale Semiconductor
HTA
Actual Throughput
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synchronization, the throughput is 55.95 MB/s. This throughput is more representative of the observed
Single Read
Single Write
Broadcast Single Write
Host DMA Read
Host DMA Write
Broadcast Host DMA Write
MSC8102ADS Board set-up includes an MSC8101 host processor.
The DSI operates in 64-bit mode and in Dual-Strobe mode.
The DCR register value is 0x28A00000 so that read prefetch is on and the
between 0.5 and 1 internal MSC8102 bus clock cycles.
The MSC8102 local bus is handling no other activities.
The MSC8102 device operates between 0 and 70 MHz.
The MSC8101 system bus operates at 66 MHz.
Read and write accesses are back-to-back and to consecutive MSC8102 memory locations
(0x0100000–M2 memory).
Host DMA means that the MSC8101 uses its DMA controller to transfer data with better performance
for back-to-back memory transfers.
The pipeline maximum depth bit has a value of 0 in the MSC8101 BCR for a pipeline depth of 1.
Single reads and writes are issued using the MSC8101 SC140 core move instructions.
Type Of Transaction
MSC8102 Asynchronous DSI Throughput, Rev. 1
Table 2. Theoretical DSI Throughput
DSI Theoretical Throughput
HTA
Based On Timings
195.83 MB/s
195.83 MB/s
213.35 MB/s
195.83 MB/s
195.83 MB/s
213.35 MB/s
signal and applying the result to Equation 1. If the MSC8101
Based On Host Programming
DSI Theoretical Throughput
And Synchronization
100.71 MB/s
55.95 MB/s
55.95 MB/s
62.95 MB/s
62.95 MB/s
71.94 MB/s
HTA
signal drive time is
Actual Throughput
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