AN2505 Freescale Semiconductor / Motorola, AN2505 Datasheet - Page 8

• Manufacturer Part Number: AN2505
• Description: MSC8102 Asynchronous DSI Throughput
• Manufacturer: Freescale Semiconductor / Motorola

Actual Throughput
4.2 Single Read Throughput
The maximum DSI single read performance is based on accesses to the MSC8102 M2 memory. Figure 5 shows the
timings obtained from the logic analyzer. The host clock for reference is the MSC8101 system bus clock by which
the UPM controls the external memory accesses. The figure illustrates the address lines, chip select, read enable
signal, and transfer acknowledge signal as it pertains to the read transaction—all in accordance with the timing
diagram illustrated in Section 2.2.1, DSI Read Timings, on page 3. The throughput for consecutive read accesses is
calculated to be 48.65 MB/s. This value translates into approximately 10.3 MSC8101 bus clock cycles and is
averaged over four consecutive read transactions. Since the MSC8101 core issues the transactions with a move
instruction, the SC140 core stalls for the duration of the transaction. If the SC140 core operates three times faster
than the system bus clock, the SC140 core stalls for 10.3 × 3 = 30.9 core clock cycles.
4.3 Single Write Throughput
The maximum DSI single write performance is based on timings obtained using a logic analyzer after writing to
consecutive memory addresses. Figure 6 shows the results obtained from the logic analyzer, with the host clock
operating at 66 MHz. The figure illustrates the address lines, chip select, write enable strobe, and transfer
acknowledge signal as it pertains to the timing diagram in Section 2.2.2, DSI Write Timings, on page 4. The
throughput for consecutive write accesses is calculated to be 45.96 MB/s. This value translates into approximately
10.95 MSC8101 bus clock cycles and is averaged over four consecutive write transactions to the MSC8102 M2
memory. As with the read transaction, the MSC8101 core issues the transaction with a move instruction. The
SC140 core stalls for the duration of the transaction. If the SC140 core operates three times faster than the system
bus clock, the SC140 core stalls for 10.95 × 3 = 32.85 core clock cycles.
8
•
•
Note: The system bus clock is not connected to the MSC8102 but is illustrated in Figure 5 because the
Note: The
Host 60x System Bus Clock
Throughput measurements for host DMA accesses are taken over an average of four transactions.
Throughput measurements for single reads and writes are taken over an average of four transactions.
memory controller signals are based on this clock.
to extend the MSC8101 read and write accesses until the MSC8102 DSI can complete the
transaction. The time between the deassertion of the chip select and the next address is
representative of the host transfer acknowledge extending the write transaction.
HTA
HTA/UPMWAIT
signal is connected to the MSC8101
HRW/POE
HCS/CS4
Address
MSC8102 Asynchronous DSI Throughput, Rev. 1
Figure 5. Asynchronous Single Read
UPMWAIT
signal. The transfer acknowledge is used
Freescale Semiconductor