AN2681 Freescale Semiconductor / Motorola, AN2681 Datasheet - Page 4

• Manufacturer Part Number: AN2681
• Description: 1-Wire Interface on the i.MX21 Application Processor
• Manufacturer: Freescale Semiconductor / Motorola

i.MX21 1-Wire Hardware Interface
2.1 Control Register
The 16-bit Control register is used to drive the communication with the 1-Wire external device.
The programmer only needs to set the bits as specified in the Control register when communicating with
the 1-Wire device and then signal the self-clearing bits when the transaction is complete.
4
Reserved Bits
Bits 15-8
Name
RDST
WR0
WR1
RPP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PST
2-0
RESET PRESENCE PULSE—This bit is
self-clearing, and is cleared after the
detection of the presence pulse from the 1-
Wire interface.
PRESENCE STATUS—This bit is valid
after the RPP bit is self-cleared.
WRITE 0—This bit is self-clearing and will
be cleared when the write of the bit is
complete.
WRITE 1 / READ—This bit is self-clearing
and will be cleared when the write of the bit
is complete. This also reads the bit
because Write 1 and Read timings are
identical. The value of the read bit is stored
in RDST, and is valid after WR1/RD is self-
cleared.
READ STATUS—This bit is valid after the
WR1/RD bit is self-cleared.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 2.
Reserved Bits
Reserved bits
Description
MC9328MX21 Application Note
Go to: www.freescale.com
Control Register Description
0 = Do nothing / pulse complete.
1 = Generate Reset Pulse and sample for
DS2502 presence pulse.
This bit is self-clearing and will be cleared
after the presence is detected.
0 = Device not present.
1 = Device present.
This bit is valid after the RPP bit is self-
cleared.
0 = Do nothing / Write sequence complete.
1 = Write a 0 bit to the interface.
This bit is self-clearing and will be cleared
when the write of the bit is complete.
0 = Do nothing / Write sequence complete.
1 = Write a 1 bit to the interface.
This bit is self-clearing and will be cleared
when the write of the bit is complete. When
used for a Read operation, the read bit is
stored in RDST, and is valid after WR1/RD
is self-cleared.
0 = A 0 was sampled during a read.
1 = A 1 was sampled during a read.
This bit is valid after the WR1/RD bit is self-
cleared.
Settings
N/A
N/A
MOTOROLA