AN2681 Freescale Semiconductor / Motorola, AN2681 Datasheet - Page 6

• Manufacturer Part Number: AN2681
• Description: 1-Wire Interface on the i.MX21 Application Processor
• Manufacturer: Freescale Semiconductor / Motorola

Configuration
3 Configuration
The following settings must be configured to ensure proper operation for the 1-Wire interface.
6
Register Name
TIME_DIVIDER
AIPI_PSR0
AIPI_PSR1
PTE_GIUS
MPCTL0
MPCTL1
MPCTL1
PCCR0
GPR_E
PCCR1
CSCR
CSCR
The errata document for the i.MX21 reference manual, MC9328MX21
Chip Errata-Rev 0, 2/6/2004 (order number MC9328MX21CE/D), notes
that the BCLKDIV parameter must equal ‘0010’ so that HCLK = FCLK
/ (BCLKDIV+1) = FCLK / 3, and that IPDIV parameter must equal 1, so
that IPG_CLOCK = HCLK / (IPDIV+1) = HCLK / 2.
Set MCU & System PLL (MPLL) value.
Set BRMO, which affects jitter
performance of the MPLL.
Scale the MPLL by a factor between 1
and 4 to set FCLK. Configure HCLK by
setting BCLKDIV, which divides FCLK to
generate HCLK. Configure IPDIV, the
HCLK divider that generates
IPG_CLOCK, the clock to the 1-Wire
interface.
HCLK = FCLK / (BCLKDIV+1)
IPG_CLOCK = HCLK / (IPDIV+1)
Restart the MPLL for the settings to take
effect.
The read-only Lock Flag (LF) in the
MPCTL1 register indicates whether the
MPLL output is valid. This bit must be high
before using the 1-Wire interface.
Enable GPIO.
Configure GPIO port E for 1-Wire use.
Configure the AIPI for 16-bit
communication, since the 1-Wire registers
are 16-bit wide.
Enable the ipg_clock to the 1-Wire
module.
Set the value such that
IPG_CLOCK / (TIME_DIVIDER+1) = 1
MHz. A 1-Wire clock as close to 1 MHz as
possible is required for proper operation.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5.
Description
MC9328MX21 Application Note
Go to: www.freescale.com
Configuration Settings
NOTE:
See Chapter 7 of the MC9328MX21
Application Processor Reference Manual,
Draft Rev. 1.10, 2/23/2004, for information
on these registers.
Bits [15-14]: PRESC is the 2-bit scaling
factor to generate FCLK. 00 = divider is 1,
… 11 = divider is 4.
Bits [13-10]: BCLKDIV is the divider that
generates HCLK. Must equal ‘0010’
(divider is 3). (See note below)
Bit 9: IPDIV is the divider that generates
the clock to the 1-Wire™. Must equal ‘1’
(divider is 2). (See note below)
Bit 21 of CSCR: Set MPLL_RESTART to
restart the MPLL at the new frequency.
Bit 15 of MPCTL1: LF will be set when the
restart has completed.
Bit 11: GPIO_EN must be set.
Clear Bit 16 of PTE_GIUS, and set Bit 16
of GRP_E.
Set AIPI_PSR0 Bit 9, and clear AIPI_PSR1
bit 9.
Set Bit 31.
Bits[7-0]: 0 = Divider is 1
1 = Divider is 2
…
FF = Divider is 256.
Settings
MOTOROLA