EM6520 EM Microelectronic, EM6520 Datasheet - Page 10

• Manufacturer Part Number: EM6520
• Description: MFP version of EM6620 Ultra Low Power Microcontroller 4x8 LCD Driver
• Manufacturer: EM Microelectronic

4.3 Digital Watchdog Timer Reset
The Digital Watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It will
generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by
activating an inhibit digital watchdog bit ( NoLogicWD ) located in RegVLDCntl . At power up, and after any
system reset, the watchdog timer is activated.
If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the system reset
signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the
watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 KHz), or a
system reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and
timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer
operates also in the standby mode and thus, to avoid a system reset, standby should not be active for more
than 2.5 seconds.
From a System Reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog
timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds. It
is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the watchdog every
second.
It is possible to read the current status of the watchdog timer in RegSysCntl2 . After watchdog reset, the
counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’, {WDVal1 WDVal0}. When reaching the
‘11’ state, the watchdog reset will be active within ½ second. The watchdog reset activates the system reset
which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore always reads ‘0’.
Table 4.3.1 Watchdog timer register RegSysCntl2
4.4 CPU State after Reset
Reset initializes the CPU as shown in Table 4.4.1 below.
Table 4.4.1 Initial CPU value after Reset.
EM Microelectronic-Marin SA CH-2074 Marin, Switzerland, Tel. [phone], Fax. [phone]
10
Bit
3
2
1
0
Program counter 0
Program counter 1
Program counter 2
Periphery registers
Instruction register
Index register
Stack pointer
Carry flag
Zero flag
Name
Halt
Name
WDReset
SleepEn
WDVal1
WDVal0
Reset
0
0
0
0
Bits
12
12
12
16
2
7
1
1
1
4
R/W
R/W
R/W
R
R
Symbol
Reg.....
HALT
PC1
PC2
PC0
CY
SP
IR
IX
Z
Description
Reset the Watchdog
1 -> Resets the Logic Watchdog
0 -> no action
The Read value is always '0'
See Operating modes (sleep)
Watchdog timer data 1/4 ck[1]
Watchdog timer data 1/2 ck[1]
See peripheral memory map
$000 (as a result of Jump 0)
© EM Microelectonic-Marin SA , 12/98 Rev. A/246
A COMPANY OF
SP[0] selected
Initial Value
Undefined
Undefined
Undefined
Undefined
Undefined
Jump 0
0
EM6520