EM6520 EM Microelectronic, EM6520 Datasheet - Page 14

• Manufacturer Part Number: EM6520
• Description: MFP version of EM6620 Ultra Low Power Microcontroller 4x8 LCD Driver
• Manufacturer: EM Microelectronic

6.2 Port A
The EM6520 has one four bit general purpose CMOS input port. The port A input can be read at any time, pull-
up or pull-down resistors can be chosen by metal mask (ROM version only). All selections concerning port A are
bit-wise executable. I.e. Pull-up on PA[2], pull-down on PA[0], positive IRQ edge on PA[0] but negative on PA[1],
etc.
In sleep mode the port A inputs are continuously monitored to match the input reset condition which will
immediately wake up the EM6520. The pull-up or pull-down resistors remain active as defined in the option
register.
Figure 10. Input Port A Configuration
6.2.1 IRQ on Port A
For interrupt request generation (IRQ) one can choose direct or debounced input and positive or negative edge
IRQ triggering. With the debouncer selected ( OPtDebIntPA ) the input must be stable for two rising edges of
the selected debouncer clock ( RegPresc ). This means a worst case of 16ms(default) or 2ms (0.25ms by metal
mask) with a system clock of 32kHz.
Either a positive or a negative edge on the port A inputs - after debouncer or not - can generate an interrupt
request. This selection is done in the option register OPTIntEdgPA.
All four bits of port A can provide an IRQ, each pin with its own interrupt mask bit in the RegIRQMask1 register.
When an IRQ occurs, inspection of the RegIRQ1 , RegIRQ2 and RegIRQ3 registers allow the interrupt to be
identified and treated.
At power on or after any reset the RegIRQMask1 is set to 0, thus disabling any input interrupt. A new interrupt is
only stored with the next active edge after the corresponding interrupt mask is cleared. See also the interrupt
chapter 9.
It is recommended to mask the port A IRQ’s while one changes the selected IRQ edge. Else one may generate
a IRQ (Software IRQ). I.e. PA[0] on ‘0’ then changing from positive to negative edge selection on PA[0] will
immediately trigger an IRQPA[0] if the IRQ was not masked.
EM Microelectronic-Marin SA CH-2074 Marin, Switzerland, Tel. [phone], Fax. [phone]
14
VBAT
(VDD
VSS
Mask opt
MPAPD[n]
)
Mask opt
MPAPU[n]
PA[n]terminal
Ck[8]
Debouncer
Ck[11] or Ck[14]
NoDebIntPA[n]=1
© EM Microelectonic-Marin SA , 12/98 Rev. A/246
A COMPANY OF
IntEdgPA[n]=0
EM6520
PA3 for the
Millisecond
Counter
IRQPA[3:0]
NoPull[n]
DB[3:0]
PA0, PA3
for 10-bit
Counter
µP TestVar