SSD1859 Solomon Systech, SSD1859 Datasheet - Page 11

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SSD1859

Manufacturer Part Number
SSD1859
Description
128 x 80 STN LCD Segment / Common 4 G/S Drive
Manufacturer
Solomon Systech
Datasheet
6. PIN DESCRIPTIONS
This pin is reset signal input. When the pin is low, initialization of the chip is executed.
PS0, PS1
PS0 and PS1 determine the interface protocol between the driver and MCU. Refer to the following table
for details.
This pin is chip select input. The chip is enabled for display data/command transfer only when
low.
D
This input pin is to identify display data/command cycle. When the pin is high, the data written to the
driver will be written into display RAM. When the pin is low, the data will be interpreted as command.
This pin must be connected to VSS when 3-lines SPI interface is used.
R
This pin is microprocessor interface signal. When 6800 interface mode is selected (by PS0 and PS1),
the signal indicates read mode when high and write mode when low. When 8080 interface mode is
selected (by PS0 and PS1), a data write operation is initiated when
selected.
E
This pin is microprocessor interface signal. When 6800 interface mode is selected (by PS0 and PS1), a
data operation is initiated when
selected (PS0 and PS1), a data read operation is initiated when
D0-D7
These pins are 8-bit bi-directional data/command bus to be connected to the microprocessor’s data bus.
When serial mode is selected, D7 is the serial data input SDA and D6 is the serial clock input SCK.
INTRS
This pin is an input pin to enable the internal resistor network for the voltage regulator when INTRS is
high. When external regulator is used, this pin must be connected to VSS, and external resistor R1/R2
should be connected to VOUT, VR and VSS.
VDD
This pin is power supply.
VSS
This is a logic ground pin. It must connect to GND from external supply.
RES
CS
SSD1859
(
/
/
W
RD
PS0
L
L
H
H
C
(
)
WR
PS1
L
H
L
H
)
Rev 1.0
Interface
3-wire SPI (write only)
4-wire SPI (write only)
8080 parallel interface (read and write allowed)
6800 parallel interface (read and write allowed)
P 11/48 Dec 2003
E( RD )
is high and the chip is selected. When 8080 interface mode is
E( RD )
R/ W ( WR )
is low and the chip is selected.
is low and the chip is
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www.DataSheet4U.com
CS
is

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