UPA2753GR NEC, UPA2753GR Datasheet

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UPA2753GR

Manufacturer Part Number
UPA2753GR
Description
SWITCHING N- AND P-CHANNEL POWER MOS FET
Manufacturer
NEC
Datasheet
1.UPA2753GR.pdf (8 pages)

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Part Number:
UPA2753GR
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Document No. G15782EJ1V0DS00 (1st edition)
Date Published February 2002 NS CP(K)
Printed in Japan
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS (T
Remark
DESCRIPTION
Transistor designed for DC/DC converters and power
management applications of notebook computers.
FEATURES
Drain to Source Voltage (V
Gate to Source Voltage (V
Drain Current (DC)
Drain Current (pulse)
Total Power Dissipation (1 unit)
Total Power Dissipation (2 unit)
Channel Temperature
Storage Temperature
Single Avalanche Current
Single Avalanche Energy
Notes 1. PW
The PA2753GR is Dual N-Channel MOS Field Effect
Dual chip type
Low on-state resistance
R
R
R
Low C
Built-in G - S protection diode
Small and surface mount package (Power SOP8)
DS(on)1
DS(on)2
DS(on)3
PART NUMBER
2. T
3. Starting T
PA2753GR
iss
= 21.4 m
= 31.6 m
= 36.4 m
The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
: C
A
= 25°C, Mounted on ceramic substrate of 2000 mm
iss
= 620 pF TYP.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
10 s, Duty Cycle
ch
MAX. (V
MAX. (V
MAX. (V
Note1
= 25°C, V
Note3
DS
Note3
GS
= 0 V)
GS
GS
GS
= 0 V)
Note2
Note2
DD
= 10 V, I
= 4.5 V, I
= 4.0 V, I
N-CHANNEL POWER MOS FET
= 15 V, R
Power SOP8
PACKAGE
1%
D
A
D
D
= 4.0 A)
= 25°C, All terminals are connected.)
= 4.0 A)
= 4.0 A)
G
= 25
DATA SHEET
SWITCHING
I
D(pulse)
V
I
V
D(DC)
T
E
, V
T
P
P
I
DSS
GSS
AS
stg
AS
ch
T
T
GS
MOS FIELD EFFECT TRANSISTOR
= 20
–55 to + 150
2
150
1.7
2.0
6.4
30
8.0
x 2.2 mm
20
32
8
0 V
PACKAGE DRAWING (Unit: mm)
8
1
5.37 Max.
mJ
0.40
°C
°C
W
W
1.27
V
V
A
A
A
+0.10
–0.05
0.78 Max.
5
4
PA2753GR
0.12 M
EQUIVALENT CIRCUIT
Gate
Gate
Protection
Diode
1
2
7, 8
3
4
5, 6
0.5 ±0.2
; Source 1
; Gate 1
; Drain 1
; Source 2
; Gate 2
; Drain 2
(1/2 Circuit)
6.0 ±0.3
©
4.4
Source
Drain
0.8
Body
Diode
0.10
2001

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UPA2753GR Summary of contents

Page 1

... DD Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version ...

Page 2

... DSS Starting T TEST CIRCUIT 3 GATE CHARGE D.U. PG 25°C, All terminals are connected.) A SYMBOL TEST CONDITIONS DSS GSS GS(off ...

Page 3

TYPICAL CHARACTERISTICS (T A FORWARD TRANSFER CHARACTERISTICS 100 150˚ 75˚ 25˚ 25˚C A 0.1 0. Gate to Source Voltage - V ...

Page 4

DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 100 T - Channel Temperature - ˚C ch CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 10000 ...

Page 5

DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 100 120 140 160 T - Ambient Temperature - ˚C A FORWARD BIAS SAFE OPERATING AREA 100 T = 25˚ ...

Page 6

SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD 100 Starting 100 L - Inductive Load - H ...

Page 7

Data Sheet G15782EJ1V0DS PA2753GR 7 ...

Page 8

... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others ...

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