STW81100 STMicroelectronics, STW81100 Datasheet - Page 12

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STW81100

Manufacturer Part Number
STW81100
Description
MULTI-BAND RF FREQUENCY SYNTHESIZER
Manufacturer
STMicroelectronics
Datasheet

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STW81100
7.6 Lock Detect
This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found
to be shorter than the fixed delay (roughly 5 ns). Lock Detect signal is high when the PLL is locked.
When Power Down is activated, Lock Detect is let to high level (Lock Detect consumes current only during
PLL transients).
7.7 Change Pump
This block drives two matched current sources, Iup and Idown, which are controlled respectively by UP
and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (to
be connected to the REXT input pin) and a selection among 8 by a 3 bit word.
The minimum value of the output current is: I
Table 8. Current Value vs Selection
Note: The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are forced to VDD/2.
Figure 15. Loop Filter Connection
12/23
CPSEL2
0
0
0
0
1
1
1
1
CPSEL1
0
0
1
1
0
0
1
1
VDD
BUF
BUF
CPSEL0
0
1
0
1
0
1
0
1
Charge
Pump
MIN
= 2*VBG/REXT (VBG~1.17 V)
Cal bit
Current
2*I
3*I
4*I
5*I
6*I
7*I
8*I
I
MIN
VCTRL
MIN
MIN
MIN
MIN
MIN
MIN
MIN
ICP
C3
C3
R1
C1
R3
R3
Value for REXT=9.1 KΩ
C2
C2
1.25 mA
0.25 mA
0.50 mA
0.75 mA
1.00 mA
1.50 mA
1.75 mA
2.00 mA

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