AD8191 Analog Devices, AD8191 Datasheet - Page 13

• Manufacturer Part Number: AD8191
• Description: 4:1 DVI/HDMI Switch with Equalization Preliminary Data Sheet (Rev. PrJ, 8/2006)
• Manufacturer: Analog Devices

Preliminary Technical Data
PARALLEL INTERFACE CONFIGURATION REGISTERS
The parallel interface configuration registers can be directly written using the pins PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO
and PP_OCL.
Table 24. Parallel Interface Register Map
Name
High-speed
Device Modes
Auxiliary
Device
Modes
Receiver
Settings
Input Term.
Pulse 1
Input Term.
Pulse 2
Receive
Equalizer 1
Receive
Equalizer 2
Transmitter
Settings
HIGH-SPEED DEVICE MODES REGISTER
The high-speed (TMDS) switching mode is fixed to Quad mode
when using the parallel interface.
PP_EN:
Table 25. PP_EN Description
PP_CH[1:0]:
Table 26. Quad High-speed Switch Mode Mapping
AUXILIARY DEVICE MODES REGISTER
The auxiliary (low-speed) switch is always enabled and the
auxiliary switching mode is fixed to Quad mode when using the
parallel interface.
PP_EN
0b
1b
PP_CH[1:0]
00b
01b
10b
11b
U
High-speed (TMDS) channels enable bit
Description
High-speed channels off, low power/standby mode
High-speed channels on
U
High-speed (TMDS) switch source select bus
Bit 7
PP_EQ
PP_EQ
O[3:0]
A[3:0]
B[3:0]
C[3:0]
D[3:0]
0
0
Bit 6
High-speed
switch enable
PP_EN
Auxiliary
switch enable
1
0
0
PP_EQ
PP_EQ
Description
High-speed source A switched to
output
High-speed source B switched to
output
High-speed source C switched to
output
High-speed source D switched to
output
Bit 5
High-speed switching mode
select (Quad)
Auxiliary switching mode
select (Quad)
0
0
0
PP_EQ
PP_EQ
0
Sources A and B input termination pulse-on-source-switch select (termination always on)
Sources C and D input termination pulse-on-source-switch select (termination always on)
Bit 4
0
0
0
0
PP_EQ
PP_EQ
Sources A and B input equalization level select
Sources C and D input equalization level select
Rev. PrJ | Page 13 of 29
Bit 3
0
0
0
0
PP_EQ
PP_EQ
Output pre-emphasis level select
PP_PE[1]
PP_CH[1:0]:
Table 27. Quad Auxiliary Switch Mode Mapping
RECEIVER SETTINGS REGISTER
High-speed (TMDS) channels input termination is fixed to on
when using the parallel interface.
INPUT TERMINATION PULSE REGISTERS 1 AND 2
High-speed input (TMDS) channels pulse-on-source switching
fixed to off when using the parallel interface.
RECEIVE EQUALIZER REGISTERS 1 AND 2
PP_EQ:
The input equalization cannot be set individually (per channel)
when using the parallel interface; one equalization setting
affects all input channels.
PP_CH[1:0]
00b
01b
10b
11b
Bit 2
0
0
0
0
PP_EQ
PP_EQ
PP_PE[0]
U
High-speed (TMDS) inputs equalization level select bit.
U
Auxiliary switch source select bus
Auxiliary switch source select
AUX_COM[3:0]
AUX_A[3:0]
AUX_B[3:0]0
AUX_C[3:0]
AUX_D[3:0]
High-speed source select
Bit 1
PP_CH[1]
PP_CH[1]
0
0
PP_EQ
PP_EQ
Output term. on/off
select
PP_OTO
Auxiliary source A switched
to output
Auxiliary source B switched
to output
Auxiliary source C switched
to output
Auxiliary source D switched
to output
Description
Bit 0
PP_CH[0]
PP_CH[0]
Input term. on/off select
(term. always on)
1
0
0
PP_EQ
PP_EQ
Output current level
select
PP_OCL
AD8191